The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jun. 07, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Chieh-Lung Lai, Taichung, TW;

Meng-Liang Lin, Hsinchu, TW;

Hsien-Wei Chen, Hsinchu, TW;

Shin-Puu Jeng, Po-Shan Village, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/3192 (2013.01); H01L 21/568 (2013.01); H01L 23/29 (2013.01); H01L 23/291 (2013.01); H01L 23/298 (2013.01); H01L 23/3185 (2013.01); H01L 23/562 (2013.01); H01L 24/19 (2013.01); H01L 24/80 (2013.01); H01L 24/81 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 80/00 (2023.02); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/20106 (2013.01); H01L 2924/20107 (2013.01);
Abstract

A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the top die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least −100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.


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