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For the Inventor, By the Inventor

Richardson, TX, United States of America

Mahalingam Nandakumar

This inventor holds 90 USPTO granted patents and 18 published patent applications and 2 EPO patents, primarily in Semiconductor Devices (CPC class H01L21-26513). Top assignees: Texas Instruments Corporation, Texas Instruments Incorpated. Active years: 1999-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mahalingam Nandakumar. Retrieved from https://idiyas.com/inventor/mahalingam-nandakumar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 90 

% Patents Active = 95.6

 

Average Co-Inventor Count = 1.8

ph-index = 10

Forward Citations = 428(Granted Patents)

Forward Citations (Not Self Cited) = 394(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Plano, TX (US) (2001 - 2004)
  • Richardson, TX (US) (1999 - 2024)

Company Filing History:

goldMedal89 out of 29,888 
 
Texas Instruments Corporation
 patents
silverMedal1 out of 3 
 
Texas Instruments Incorpated
 patents

Years Active: 1999-2026

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Areas of Expertise:
MOS Transistors
Threshold Voltage Mismatch
Low Noise Transistor
Resistors
Capacitors
Dielectric Layers
Implantation Treatment
Diffusion Suppression
High Resistance Resistors
Fringe Capacitance
Dopant Dose Optimization
Integrated Circuits
90 patents (USPTO):Explore Patents
1. 12765042 - Reducing cross-wafer variability for minimum width resistors (2026-10-13),
2. 12635229 - Zero tempco resistor (2026-05-19),
3. 12588236 - Two-rotation gate-edge diode leakage reduction for MOS transistors (2026-03-24),
4. 12512322 - Small grain size polysilicon engineering for threshold voltage mismatch improvement (2025-12-30),
5. 12500117 - Shallow trench isolation structure with nitride pullback by implantation treatment (2025-12-16),
6. 12494425 - Integration scheme to build resistor, capacitor, efuse using silicon-rich dielectric layer as a base dielectric (2025-12-09),
7. 12484236 - Polysilicon resistor implant for reduced resistance temperature coefficient variability (2025-11-25),
8. 12453111 - Channel stop and well dopant migration control implant for reduced MOS threshold voltage mismatch (2025-10-21),
9. 12408352 - Advanced poly resistor and CMOS transistor (2025-09-02),
10. 12317583 - Semiconductor device with low noise transistor and low temperature coefficient resistor (2025-05-27),
11. 12154987 - Damage implantation of cap layer (2024-11-26),
12. 12154901 - Semiconductor device with diffusion suppression and LDD implants and an embedded non-LDD semiconductor device (2024-11-26),
13. 12107117 - High resistance poly resistor (2024-10-01),
14. 12015057 - Carbon, nitrogen and/or fluorine co-implants for low resistance transistors (2024-06-18),
15. 12009423 - Two-rotation gate-edge diode leakage reduction for MOS transistors (2024-06-11),

Title: Mahalingam Nandakumar - Innovative Inventor from Richardson, TX

Introduction: Mahalingam Nandakumar is a highly skilled inventor based in Richardson, Texas, known for his groundbreaking contributions to various technological fields.

Latest Patents: Mahalingam Nandakumar holds several patents in the areas of artificial intelligence, renewable energy, and telecommunications, showcasing his diverse expertise and innovative mindset.

Career Highlights: With a career spanning over two decades, Nandakumar has worked for leading tech companies, where he spearheaded research and development projects that resulted in cutting-edge inventions.

Collaborations: Throughout his career, Mahalingam Nandakumar has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and excellence in the projects he undertakes.

Conclusion: Mahalingam Nandakumar's passion for innovation and his relentless pursuit of technological advancement make him a standout figure in the world of inventors, with a legacy that continues to inspire future generations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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