The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Mar. 23, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Mahalingam Nandakumar, Richardson, TX (US);

Brian Edward Hornung, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/2253 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/266 (2013.01); H01L 21/823418 (2013.01); H01L 29/0847 (2013.01); H01L 29/66492 (2013.01); H01L 29/7833 (2013.01);
Abstract

The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.


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