The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jun. 30, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Mahalingam Nandakumar, Richardson, TX (US);

Douglas Harvey Newman, Crowley, TX (US);

Byron Joseph Palla, Murphy, TX (US);

Haowen Bu, Lucas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/311 (2006.01); H10D 84/80 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/31111 (2013.01); H10D 84/811 (2025.01); H01L 21/31144 (2013.01);
Abstract

A semiconductor device includes a trench extending into a semiconductor layer. A liner layer is on a sidewall of the semiconductor layer within the trench. The liner layer extends from the sidewall to a top surface of the semiconductor layer. An isolation structure is within the trench. The isolation structure is between a first region of the semiconductor layer and a second region of the semiconductor layer. The semiconductor layer includes a third region that couples the first region to the second region of the semiconductor layer. The third region of the semiconductor layer is substantially free of phosphorus contamination.


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