Hsinchu, Taiwan

Jyu-Horng Shieh

This inventor holds 126 USPTO granted patents and 17 published patent applications, primarily in Semiconductor Manufacturing (CPC class H01L21-31144). Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2001-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jyu-Horng Shieh. Retrieved from https://idiyas.com/inventor/jyu-horng-shieh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 126 

% Patents Active = 80.2

Average Co-Inventor Count = 3.5

ph-index = 12

Forward Citations = 590(Granted Patents)

Forward Citations (Not Self Cited) = 514(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Hsin-chun, TW (2007)
  • Hsin-Chu, TW (2001 - 2024)

Company Filing History:


Years Active: 2001-2026

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Areas of Expertise:
Integrated Circuit
Semiconductor Device
Double Patterning
Magnetic Tunnel Junctions
Gradient Protection Layer
Interconnect Structure
Self-Aligned Via
Middle-of-Line Interconnect
DC Bias
Spacer Etching
Metal Etching Stop Layer
Damascene Structure
126 patents (USPTO):Explore Patents

Jyu-Horng Shieh: Semiconductor Innovator from Hsin-Chu, TW

With a whopping 100 patents to his name, Jyu-Horng Shieh is a renowned innovator in the semiconductor industry. His latest patents demonstrate his technical expertise and brilliance in the field of semiconductor technology.

One of his recent patents, titled "Semiconductor structure and manufacturing method of the same," describes a process for creating a magnetic tunneling junction (MTJ) layer in a semiconductor structure. The method allows for the formation of an MTJ layer that can be precisely patterned using ion beam etching techniques. This patent is a testament to Shieh's ingenuity and his contributions to the semiconductor manufacturing process.

Another notable invention by Shieh is the "Self-aligned double patterning" patent. This patent describes a method of creating spacers in a target layer to etch a pattern with high accuracy. The process involves forming first and second mandrels having different widths and then creating spacers from a spacer layer that is altered to have a greater thickness over the first mandrels. The resulting pattern has high precision due to the use of spacers with varying widths.

Jyu-Horng Shieh is employed at the Taiwan Semiconductor Manufacturing Company Limited, a world-leading semiconductor manufacturer. He works alongside other brilliant innovators such as Chih-Yuan Ting and Chia-Ying Lee. Together, they continue to push the boundaries of semiconductor technology and contribute to the advancement of the electronics industry.

Shieh's work has undoubtedly paved the way for the future of semiconductor manufacturing. His contributions to the industry have not gone unnoticed, and he continues to inspire new generations of innovators in the field of electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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