Taiwan Semiconductor Manufacturing Comp. Ltd.

Jyu-Horng Shieh

Chih-Yuan Ting

Chia-Ying Lee

Tai-Yen Peng

Yi-Nien Su

Yu-Shu Chen

Ru-Gun Liu

Sin-Yi Yang

Han-Ting Lin

Chen-Jung Wang

Shu-Huei Suen

Jeng-Shiou Chen

Hun-Jan Tao

Hui-Hsien Wei

Syun-Ming Jang Jang

Chung-Wen Wu

Chien Chung Huang

Chih-Ming Lai

Chung-Te Lin

Shih-Ming Chang

Ming-Feng Shieh

Ken-Hsien Hsieh

Minghsing Tsai

Ju-Wang Hsu

Jang-Shiang Tsai

Qiang Fu

Chien-Min Lee

Han-Ting Tsai

Sheng-Liang Pan

Chien-Chung Huang

Pin-Ren Dai

Yu-Yu Chen

Wei-Chih Wen

Peng-Fu Hsu

Kuan-Wei Huang

Chia-Yang Hung

Jack Kuo-Ping Kuo

Shau-Lin Shue

Chung-Ju Lee

Tien-I Bao

Tsai-Sheng Gau

Cheng-Hsiung Tsai

Pei-Wen Huang

Jen-Cheng Liu

Chao-Cheng Chen

Baw-Ching Perng

Ming-Hui Chu

Huicheng Chang

Liang-Yin Chen

Ming-Hsing Tsai

Yung-Sung Yen

Chia-Cheng Chen

Wei-Liang Lin

Ming-Chung Liang

Ya Hui Chang

Yu-Tien Shen

Bing-Hung Chen

Ya-Wen Yeh

Yi-Chun Huang

Chia-Fong Chang

Tsung-Hsien Chang

Chia Ying Lee

Chia-Shiung Tsai

Wen-Chih Chiou

Mei-Yun Wang

Chih-Hsin Ko

Yung-Cheng Lu

Fu-Kai Yang

Chung-Chi Ko

Chia-Jen Chen

Chih-Hao Chen

Chang-Yun Chang

Kuo-Yi Chao

Chao-Hsun Wang

Chen-Yuan Kao

Chen-Nan Yeh

Yuan-Hung Chiu

Wen-Yen Chen

Bor-Wen Chan

Chang-Sheng Lin

Yu-Feng Yin

Chun-Li Chou

Huang-Ming Chen

Feng-Yu Chang

Chien-Chih Chiu

Shao-Jyun Wu

Wen-Kuo Hsieh

Yi-Chen Huang

Sheng-Da Liu

Chien-Han Chen

Zhong Tang Xuan

Shih-Yu Chang

Pang-Sheng Chang

Chia-Sheng Chang

Chia-Shia Tsai

Ju-Chien Chiang

Li-Chi Chao

Bor-Shyang Lin

A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.

Integrated circuit with conductive line having line-ends

A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Interconnect line for semiconductor device

An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.

Integrated circuit

A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.

Dual damascene structure in forming source/drain contacts

A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Method of forming a semiconductor device

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

DC bias in plasma process

A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Gradient protection layer in MTJ manufacturing

A method includes forming a first mandrel and a second mandrel over a dielectric layer, and forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively. The first spacer and the second spacer are next to each other with a space in between. The dielectric layer is etched to form an opening in the dielectric layer, with the opening being overlapped by the space, and with the first spacer and the second spacer being used as a part of an etching mask in the etching. A conductive material is filled into the opening. A planarization process is performed on the conductive material.

Self-aligned via formation using spacers

An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.

Integrated circuit and method for manufacturing the same

In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Method of manufacturing semiconductor devices

Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

Middle-of-line interconnect structure having air gap and method of fabrication thereof

An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

Integrated circuit structure

A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

Self-aligned double patterning

A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Semiconductor device with magnetic tunnel junctions

The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Semiconductor structure and manufacturing method of the same

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Hsin-Chu, Taiwan

Jyu-Horng Shieh