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For the Inventor, By the Inventor

Boise, ID, United States of America

Jaspreet Singh Gandhi

LinkedIn
USPTO Granted Patents = 94 

 

Average Co-Inventor Count = 2.3

ph-index = 8

Forward Citations = 250(Granted Patents)

Forward Citations (Not Self Cited) = 220(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Milpitas, CA (US) (2018 - 2020)
  • Union City, CA (US) (2021)
  • Boise, ID (US) (2013 - 2023)
  • San Jose, CA (US) (2019 - 2024)

Company Filing History:

goldMedal69 out of 37,972 
 
Micron Technology Incorporated
 patents
silverMedal25 out of 5,008 
 
Xilinx, Inc.
 patents

Years Active: 2013-2024

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Areas of Expertise:
Thermal Management
Stacked Semiconductor Dies
Silicon Package Assembly
Interconnect Structures
High Density Routing
Chip Package Assembly
Thermal Interface Material
Memory Device Integration
Solder Joint Reliability
Multi-Die Device Structures
Conductive Vias
Through-Silicon Vias
94 patents (USPTO):Explore Patents
1. 12033980 - Thermal pads between stacked semiconductor dies and associated systems and methods (2024-07-09),
2. 12027493 - Fanout integration for stacked silicon package assembly (2024-07-02),
3. 11901300 - Universal interposer for a semiconductor package (2024-02-13),
4. 11776877 - Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths (2023-10-03),
5. 11688664 - Semiconductor device assembly with through-mold cooling channel formed in encapsulant (2023-06-27),
6. 11594462 - Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods (2023-02-28),
7. 11488936 - Stacked silicon package assembly having vertical thermal management (2022-11-01),
8. 11373989 - Package integration for laterally mounted IC dies with dissimilar solder interconnects (2022-06-28),
9. 11355412 - Stacked silicon package assembly having thermal management (2022-06-07),
10. 11315858 - Chip package assembly with enhanced solder resist crack resistance (2022-04-26),
11. 11302674 - Modular stacked silicon package assembly (2022-04-12),
12. 11282776 - High density routing for heterogeneous package integration (2022-03-22),
13. 11282775 - Chip package assembly with stress decoupled interconnect layer (2022-03-22),
14. 11217550 - Chip package assembly with enhanced interconnects and method for fabricating the same (2022-01-04),
15. 11195780 - Stacked silicon package assembly having thermal management using phase change material (2021-12-07),

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