logo

For the Inventor, By the Inventor

Boise, ID, United States of America

Jaspreet Singh Gandhi

LinkedIn

This inventor holds 96 USPTO granted patents and 16 published patent applications and 9 EPO patents, primarily in Semiconductor Packaging (CPC class H01L25-0657). Top assignees: Micron Technology Incorporated, Xilinx, Inc.. Active years: 2013-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jaspreet Singh Gandhi. Retrieved from https://idiyas.com/inventor/jaspreet-singh-gandhi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 96 

% Patents Active = 97.9

 

Average Co-Inventor Count = 2.3

ph-index = 8

Forward Citations = 275(Granted Patents)

Forward Citations (Not Self Cited) = 220(Dec 10, 2025)


Inventors with similar research interests:

🔬 See more inventors

Location History:

  • Milpitas, CA (US) (2018 - 2020)
  • Union City, CA (US) (2021)
  • Boise, ID (US) (2013 - 2023)
  • San Jose, CA (US) (2019 - 2024)

Company Filing History:

goldMedal69 out of 39,222 
 
Micron Technology Incorporated
 patents
silverMedal27 out of 5,108 
 
Xilinx, Inc.
 patents

Years Active: 2013-2026

Loading Chart...
Loading Chart...
Areas of Expertise:
Thermal Management
Stacked Die Assemblies
Interconnect Structures
Silicon Package Assembly
Cooling Channels
Solder Interconnects
High Density Routing
Modular Packaging
Thermal Interface Materials
Conductive Vias
Memory Device Integration
Test Structures
96 patents (USPTO):Explore Patents
1. 12702065 - Chip package integration with hybrid bonded bridge die (2026-08-04),
2. 12666981 - Stress-reduced package substrate and method of forming the same (2026-06-23),
3. 12033980 - Thermal pads between stacked semiconductor dies and associated systems and methods (2024-07-09),
4. 12027493 - Fanout integration for stacked silicon package assembly (2024-07-02),
5. 11901300 - Universal interposer for a semiconductor package (2024-02-13),
6. 11776877 - Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths (2023-10-03),
7. 11688664 - Semiconductor device assembly with through-mold cooling channel formed in encapsulant (2023-06-27),
8. 11594462 - Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods (2023-02-28),
9. 11488936 - Stacked silicon package assembly having vertical thermal management (2022-11-01),
10. 11373989 - Package integration for laterally mounted IC dies with dissimilar solder interconnects (2022-06-28),
11. 11355412 - Stacked silicon package assembly having thermal management (2022-06-07),
12. 11315858 - Chip package assembly with enhanced solder resist crack resistance (2022-04-26),
13. 11302674 - Modular stacked silicon package assembly (2022-04-12),
14. 11282776 - High density routing for heterogeneous package integration (2022-03-22),
15. 11282775 - Chip package assembly with stress decoupled interconnect layer (2022-03-22),

As an AI assistant specializing in innovations, inventions, inventors, patent attorneys, assignees, and patents, I must inform you that I am focusing only on these topics. If you need assistance with anything else, please let me know.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…