The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Sep. 28, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Jaspreet Singh Gandhi, San Jose, CA (US);

Gamal Refai-Ahmed, Santa Clara, CA (US);

Henley Liu, San Jose, CA (US);

Myongseob Kim, Pleasanton, CA (US);

Tien-Yu Lee, San Jose, CA (US);

Suresh Ramalingam, Fremont, CA (US);

Cheang-Whang Chang, Mountain View, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/427 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 25/065 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 21/481 (2013.01); H01L 21/4871 (2013.01); H01L 23/427 (2013.01); H01L 25/0655 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2924/165 (2013.01); H01L 2924/1631 (2013.01); H01L 2924/1632 (2013.01); H01L 2924/16251 (2013.01); H01L 2924/16315 (2013.01);
Abstract

A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.


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