The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2022
Filed:
May. 21, 2020
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Jaspreet Singh Gandhi, San Jose, CA (US);
Suresh Ramalingam, Fremont, CA (US);
William E. Allaire, West Chester, PA (US);
Hong Shi, Fremont, CA (US);
Kerry M. Pierce, Richland, WA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06586 (2013.01);
Abstract
A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.