West Linn, OR, United States of America

Janusz Rajski

This inventor holds 130 USPTO granted patents and 9 published patent applications and 15 EPO patents, primarily in Test Compression Techniques (CPC class G01R31-318547). Top assignees: Mentor Graphics Corporation, Siemens Industry Software Gmbh, Other. Active years: 1998-2026.

USPTO Granted Patents = 130 

% Patents Active = 85.4

 

Average Co-Inventor Count = 3.6

ph-index = 29

Forward Citations = 2,449(Granted Patents)

Forward Citations (Not Self Cited) = 1,452(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Wilsonville, OR (US) (2010)
  • West Linn, OR (US) (1998 - 2023)

Company Filing History:


Years Active: 1998-2026

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Areas of Expertise:
Test Compression
Built-In Self-Test
Scan Architecture
Data Streaming
Test Pattern Generation
Test Coverage
Timing-Aware Testing
Circuit Testing
Test Scheduling
Fault Simulation
Low Power Testing
Hardware Security
130 patents (USPTO):Explore Patents

Title: Janusz Rajski: Innovator Extraordinaire with 128 Patents

Introduction:

Janusz Rajski, a resident of West Linn, Oregon, has made significant contributions to the field of circuit testing and built-in self-test techniques. With an impressive record of 128 patents, Rajski is a recognized expert in his field. In this article, we explore his latest patents, career highlights, notable collaborations, and celebrate his invaluable contributions to the world of innovations and patents.

Latest Patents:

Rajski's recent patents showcase his expertise in circuit testing methodologies. One notable invention is the "Trajectory-optimized test pattern generation for built-in self-test." This patent presents a novel circuit configuration that includes a bit-flipping signal generation device, a pseudo-random test pattern generator, and scan chains, allowing for precise fault detection during testing.

Another significant invention by Rajski is the "Deterministic stellar built-in self-test" system. This patent introduces a circuit testing system that leverages shift operations, parent and child test patterns, and bit-inverting circuitry to enhance the efficiency and accuracy of circuit testing.

Career Highlights:

Rajski's remarkable career spans across various notable companies, where he has left an indelible mark. He has contributed significantly to the success of Mentor Graphics Corporation, a leading electronic design automation company. Rajski's innovative ideas and expertise have played a crucial role in advancing the company's capabilities in circuit testing and design verification.

Collaborations:

During his professional journey, Rajski has had the privilege to collaborate with exceptional individuals who share his passion for innovation. Two notable collaborators are Jerzy Tyszer and Mark A Kassab. These experts have worked closely with Rajski to develop cutting-edge solutions for circuit testing and have greatly influenced the field with their combined knowledge and expertise.

Conclusion:

Janusz Rajski's numerous patents and outstanding contributions to the world of innovation in circuit testing have solidified his position as an esteemed inventor. His latest patents demonstrate his ability to develop novel solutions that optimize built-in self-test methodologies and enhance circuit test accuracy. Rajski's career highlights and collaborations with esteemed professionals highlight his significant impact on the field of circuit testing. We applaud his remarkable achievements and eagerly anticipate his future contributions to the world of innovations and patents.

Profile summary based on public USPTO records.
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