The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Mar. 21, 2019
Applicant:

Siemens Industry Software Inc., Plano, TX (US);

Inventors:

Yingdi Liu, Wilsonville, OR (US);

Nilanjan Mukherjee, Wilsonville, OR (US);

Janusz Rajski, West Linn, OR (US);

Jerzy Tyszer, Poznan, PL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/3181 (2006.01); G01R 31/3177 (2006.01); G01R 31/3183 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318536 (2013.01); G01R 31/3177 (2013.01); G01R 31/31813 (2013.01); G01R 31/318307 (2013.01); G01R 31/318371 (2013.01); G01R 31/318385 (2013.01);
Abstract

A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.


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