Mentor Graphics Corporation

Other

Siemens Industry Software Gmbh

Janusz Rajski

Jerzy Tyszer

Mark A Kassab

Nilanjan Mukherjee

Grzegorz Mrugalski

Chen Wang

Nagesh Tamarapalli

Xijiang Lin

Yu Jane Huang

Wu-Tung Cheng

Dariusz Czysz

Kun-Han Tsai

Jedrzej Solecki

Artur Pogiel

Sylwester Milewski

Huaxing Tang

Jean-Francois Cote

Elham K Moghaddam

Jon Udell

Randy Klingenberg

Justyna Zawada

Robert Douglas Thompson

Gang Paul Chen

Manish Sharma

Dhiraj Goswami

Jakub Janicki

Martin Keim

Abu Mokhtarul Hassan

Yingdi Liu

Lukasz Rybak

Benoit Nadeau-Dostie

Amit Kumar

Thomas Hans Rinderknecht

Avijit Dutta

Mohamed Dessouky

Jay Babak Jahangiri

Wojciech Rajski

John T Chen

Bartosz Wlodarczak

Jeffrey Mayer

Przemyslaw Szczerbicki

A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.

Universal compactor architecture for testing circuits

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

Trajectory-optimized test pattern generation for built-in self-test

A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

Deterministic stellar built-in self test

The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.

Isometric control data generation for test compression

A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Layout-friendly test pattern decompressor

A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.

Flexible isometric decompressor architecture for test compression

One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers. The one, two, or three test pattern generation and encoding processes are configured to minimize active input channels for each of the compressed test patterns. A test pattern count for each of a plurality of input channel numbers is determined based on the compressed test patterns for the one or two input channel numbers, a number of active input channels for each of the compressed test patterns, and an assumption of similar input data volumes for different numbers of input channels. The test pattern count information can be employed to determine an optimal number of input channels for a test decompressor.

Prediction of test pattern counts for scan configuration determination

Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern. The hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation. Activation probabilities and observation probabilities are then determined for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates. Finally, test patterns are generated based on the activation probabilities and the observation probabilities.

Test generation using testability-based guidance

A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.

Scan cell architecture for improving test coverage and reducing test application time

Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.

Test scheduling and test access in test compression environment

A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of '1' and a specified value of '0' for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.

Signal probability-based test cube reordering and merging

Various aspects of the disclosed technology relate to streaming data to circuit blocks in a circuit. A system for streaming data in a circuit comprises a first network comprising first data channels and first interface devices and a second network comprising second data channels and second interface devices. Each of the first interface devices is coupled to ports of one of circuit blocks in the circuit and configurable to transport a plurality of equal-sized data packets consecutively. Each of the second interface devices is coupled to one of the first interface devices and configurable to transport configuration data to the first interface devices. The configuration data comprise data for determining whether or not a first interface device is activated and data for determining which bit or bits of each of the plurality of data packets to be captured, replaced, or captured and replaced by an activated first interface device.

Efficient and flexible network for streaming data in circuits

Various aspects of the disclosed technology relate to using data throttling to generate streaming data for streaming networks in circuits. A plurality of equal-sized data packets to be transported consecutively in a network to the plurality of circuit blocks are generated. The number of bits in each of the plurality of equal-sized data packets assigned to a circuit block requiring longest data loading time is equal to the number of input ports of the circuit block, while the number of bits in each of the plurality of data packets assigned to each of the rest of the plurality of circuit blocks is equal to or smaller than the number of input ports of the each of rest of the plurality of circuit blocks, determined based on the longest data loading time and data loading time for the each of rest of the plurality of circuit blocks.

Streaming networks efficiency using data throttling

Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.

Test application time reduction using capture-per-cycle test points

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Growing community of inventors

West Linn, OR, United States of America

Janusz Rajski