Singapore, Singapore

Jairus Legaspi Pisigan

This inventor holds 38 USPTO granted patents and 1 published patent application, primarily in Integrated Circuit Packaging. Top assignee: Stats Chippac Pte. Ltd.. Active years: 2010-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jairus Legaspi Pisigan. Retrieved from https://idiyas.com/inventor/jairus-legaspi-pisigan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 38 

% Patents Active = 100.0

Average Co-Inventor Count = 3.5

ph-index = 7

Forward Citations = 162(Granted Patents)


Company Filing History:


Years Active: 2010-2017

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Areas of Expertise:
Integrated Circuit
Packaging System
Stacked Die
Vertical Interconnect
Flip Chip
Leadframe
Protective Layer
Multi-layer
Bond Wire Pads
Etched Recess
Anti-peel Contact Pads
Dual Substrate
38 patents (USPTO):Explore Patents

Title: Innovations by Jairus Legaspi Pisigan in Semiconductor Technology

Introduction

Jairus Legaspi Pisigan is a notable inventor based in Singapore, SG, who has made significant contributions to the field of semiconductor technology. With a remarkable portfolio of 38 patents, Pisigan has developed several innovative solutions that enhance the functionality and efficiency of semiconductor devices.

Latest Patents

Among his latest innovations are two key patents:

1. **Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure** - This patent describes a semiconductor device created by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is strategically placed in proximity to the first die, with a second semiconductor die mounted over the second and third interconnect structures. The design ensures that the back sides of both semiconductor dies are substantially coplanar with their respective interconnect structures, optimizing space and connectivity.

2. **Semiconductor device and method of forming leadframe with notched fingers for stacking semiconductor die** - This patent involves a semiconductor device featuring a leadframe with notched fingers. A first semiconductor die is mounted over a carrier between these notched fingers. The invention also details the formation of conductive through-silicon vias (TSVs) connecting the first semiconductor die to bond wires, culminating in an encapsulated semiconductor device ready for stacking additional dies.

Career Highlights

Jairus currently works at Stats Chippac Pte. Ltd., a company renowned for its advanced semiconductor packaging solutions. His work at Stats Chippac has fostered breakthroughs in semiconductor design, making a significant impact on the industry.

Collaborations

Throughout his career, Jairus has collaborated with various talented professionals, including Zigmund Ramirez Camacho and Henry Descalzo Bathan. These collaborations have enabled the sharing of ideas and expertise, contributing to the innovative projects and patents that define his career.

Conclusion

Jairus Legaspi Pisigan continues to be a driving force in the semiconductor industry with his impressive patent portfolio and innovative solutions. His work not only showcases his talent as an inventor but also highlights the importance of collaboration in driving technological advancements. Through his contributions, he is reshaping the future of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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