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For the Inventor, By the Inventor

San Jose, CA, United States of America

Erwin E Yu

This inventor holds 27 USPTO granted patents and 7 published patent applications, primarily in Memory Devices. Top assignees: Micron Technology Incorporated, Intel Corporation. Active years: 2010-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Erwin E Yu. Retrieved from https://idiyas.com/inventor/erwin-e-yu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 

% Patents Active = 88.9

Average Co-Inventor Count = 3.8

ph-index = 3

Forward Citations = 37(Granted Patents)


Location History:

  • Santa Clara, CA (US) (2018 - 2020)
  • San Jose, CA (US) (2010 - 2024)

Company Filing History:

goldMedal23 out of 39,176 
 
Micron Technology Incorporated
 patents
silverMedal4 out of 56,290 
 
Intel Corporation
 patents

Years Active: 2010-2026

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Areas of Expertise:
Erase Operations
Memory Devices
Bias Control
Data Latch Voltage
Microelectronic Devices
Memory Array Structures
Sensing Circuit
Programming Convergence
Temperature Compensation
Dynamic Source Bounce
Verification Checks
Capacitive Characteristics
27 patents (USPTO):Explore Patents
1. 12706156 - Selective management of erase operations in memory devices that enable suspend commands (2026-08-11),
2. 12676191 - Seeding bias control for sub-block groups in a memory device (2026-07-07),
3. 12573461 - Managing sense amplifier latch and data latch voltage to reduce standby current (2026-03-10),
4. 12276686 - Apparatus for determination of capacitive and resistive characteristics of access lines (2025-04-14),
5. 12183396 - Memory array structures and methods of forming memory array structures (2024-12-31),
6. 12171096 - Microelectronic devices, and related memory devices and electronic systems (2024-12-17),
7. 12101932 - Microelectronic devices, and related memory devices and electronic systems (2024-09-24),
8. 12068037 - Managing sub-block erase operations in a memory sub-system (2024-08-20),
9. 11942159 - Selective management of erase operations in memory devices that enable suspend commands (2024-03-26),
10. 11915758 - Memory devices with four data line bias levels (2024-02-27),
11. 11862257 - Managing programming convergence associated with memory cells of a memory sub-system (2024-01-02),
12. 11749353 - Managing sub-block erase operations in a memory sub-system (2023-09-05),
13. 11562791 - Memory devices with four data line bias levels (2023-01-24),
14. 11557351 - Sense circuit to sense two states of a memory cell (2023-01-17),
15. 11557341 - Memory array structures and methods for determination of resistive characteristics of access lines (2023-01-17),

Title: Erwin E Yu: Pioneering Inventor from San Jose

Introduction: Erwin E Yu is a distinguished inventor based in San Jose, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Erwin E Yu holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his expertise in cutting-edge technologies.

Career Highlights: With a career spanning over two decades, Erwin E Yu has worked with leading tech companies, spearheading research and development projects that have led to significant advancements in the industry.

Collaborations: Throughout his career, Erwin E Yu has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and creativity in the projects he undertakes.

Conclusion: Erwin E Yu's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and technologists worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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