The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2024

Filed:

Aug. 13, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Erwin E. Yu, San Jose, CA (US);

Michele Piccardi, Cupertino, CA (US);

Surendranath C. Eruvuru, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 5/02 (2006.01); H01L 23/538 (2006.01); H01L 27/092 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); B81B 1/00 (2006.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 23/5386 (2013.01); H01L 27/092 (2013.01); H10B 43/27 (2023.02); B81B 1/00 (2013.01); B81B 2201/07 (2013.01);
Abstract

A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.


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