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For the Inventor, By the Inventor

Guilderland, NY, United States of America

Douglas C La Tulipe, Jr

This inventor holds 40 USPTO granted patents and 5 published patent applications, primarily in Semiconductor Fabrication. Top assignees: International Business Machines Corporation, Infineon Technologies Ag, Globalfoundries Inc.. Active years: 2006-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Douglas C La Tulipe, Jr. Retrieved from https://idiyas.com/inventor/douglas-c-la-tulipe-jr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 40 

% Patents Active = 42.5

Average Co-Inventor Count = 4.3

ph-index = 11

Forward Citations = 734(Granted Patents)


Location History:

  • Danbury, CT (US) (2006 - 2009)
  • New Fairfield, CT (US) (2009 - 2011)
  • Yorktown Heights, NY (US) (2015)
  • Albany, NY (US) (2011 - 2016)
  • Guilderland, NY (US) (2010 - 2017)

Company Filing History:

goldMedal34 out of 166,409 
 
International Business Machines Corporation
 patents
silverMedal8 out of 15,036 
 
Infineon Technologies Ag
 patents
bronzeMedal5 out of 5,671 
 
Globalfoundries Inc.
 patents
4. 1 out of 59 
 
Globalfoundries U.S. 2 LLC
 patents
where one patent can have more than one assignee

Years Active: 2006-2017

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Areas of Expertise:
Semiconductor Fabrication
3D Integration
Wafer Bonding
Ultra-Deep Vias
CMOS Technology
Thin Film Structures
Transistor Wiring
Dielectric Materials
Hardmask Properties
Strained SOI Substrates
Membrane Technology
Bonding Techniques
40 patents (USPTO):Explore Patents
1. 9620481 - Substrate bonding with diffusion barrier structures (2017-04-11),
2. 9583628 - Semiconductor device with a low-K spacer and method of forming the same (2017-02-28),
3. 9543229 - Combination of TSV and back side wiring in 3D integration (2017-01-10),
4. 9536809 - Combination of TSV and back side wiring in 3D integration (2017-01-03),
5. 9412620 - Three-dimensional integrated circuit device fabrication including wafer scale membrane (2016-08-09),
6. 9318375 - Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias (2016-04-19),
7. 9219129 - Inverted thin channel mosfet with self-aligned expanded source/drain (2015-12-22),
8. 9190303 - Reducing wafer bonding misalignment by varying thermal treatment prior to bonding (2015-11-17),
9. 9171749 - Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler wafer (2015-10-27),
10. 9064937 - Substrate bonding with diffusion barrier structures (2015-06-23),
11. 9059039 - Reducing wafer bonding misalignment by varying thermal treatment prior to bonding (2015-06-16),
12. 9029238 - Advanced handler wafer bonding and debonding (2015-05-12),
13. 8963278 - Three-dimensional integrated circuit device using a wafer scale membrane (2015-02-24),
14. 8946007 - Inverted thin channel mosfet with self-aligned expanded source/drain (2015-02-03),
15. 8940554 - Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness (2015-01-27),

Title: **Douglas C La Tulipe, Jr: Innovator in Semiconductor Technology**

Introduction

Douglas C La Tulipe, Jr. is a prominent inventor based in Guilderland, NY, with an impressive portfolio of 40 patents. He has made significant contributions to the field of semiconductor technology, particularly with innovations that enhance the performance and reliability of electronic devices.

Latest Patents

Among his latest inventions, La Tulipe has introduced advanced methods for substrate bonding. His patent on "Substrate bonding with diffusion barrier structures" outlines a technique wherein a metallic dopant element, possessing a greater oxygen affinity than copper, is introduced into the surfaces of copper-based metal pads. This innovation helps in forming a dopant-metal silicate layer at the interface of two substrates, functioning effectively as an oxygen barrier and adhesion material layer. Furthermore, he has developed a semiconductor device featuring a low-K spacer, described in his patent "Semiconductor device with a low-K spacer and method of forming the same." This device includes a semiconductor substrate and a gate stack that optimally utilizes low-k spacers for improved efficiency.

Career Highlights

La Tulipe has had a distinguished career working with renowned companies such as International Business Machines Corporation (IBM) and Infineon Technologies AG. His experience at these leading tech firms has propelled his innovative efforts in semiconductor technology, allowing him to be at the forefront of various advancements.

Collaborations

Throughout his career, La Tulipe has collaborated with notable coworkers, including Spyridon Skordas and Kevin R Winstel. These collaborative efforts have contributed to the development of cutting-edge technologies in the semiconductor sphere, showcasing his ability to work effectively within a team of skilled professionals.

Conclusion

Douglas C La Tulipe, Jr. stands out as an influential inventor in the realm of semiconductor technology. With 40 patents to his name, his work has paved the way for innovations that enhance device performance and reliability. His contributions, along with his collaboration with industry leaders, continue to shape the future of technology in significant ways.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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