The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8946007 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 03, 2015

Filed:

Feb. 07, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Bruce B. Doris, Brewster, NY (US);

Kangguo Cheng, Guilderland, NY (US);

Ali Khakifirooz, Slingerlands, NY (US);

Douglas C. La Tulipe, Jr., Guilderland, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 21/74 (2006.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 29/66636 (2013.01); H01L 21/743 (2013.01); H01L 29/7848 (2013.01); H01L 29/66545 (2013.01); H01L 27/1203 (2013.01); H01L 29/78 (2013.01); H01L 27/12 (2013.01);
Abstract

After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.


Find Patent Forward Citations

Doris, Bruce. (2015). Inverted thin channel mosfet with self-aligned expanded source/drain (U.S. Patent No. 8946007). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8946007

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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