The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Aug. 30, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Pooja R. Batra, White Plains, NY (US);

John W. Golz, Manassas, VA (US);

Subramanian S. Iyer, Mount Kisco, NY (US);

Douglas C. La Tulipe, Jr., Guilderland, NY (US);

Spyridon Skordas, Wappingers Falls, NY (US);

Kevin R. Winstel, East Greenbush, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 21/768 (2006.01); H01L 25/00 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76898 (2013.01); H01L 23/528 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/29082 (2013.01); H01L 2224/32145 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/14 (2013.01);
Abstract

The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.


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