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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9412620 B1

PDFFull Text
Date of Patent:
Aug. 09, 2016

Filed:

Jan. 15, 2015

Three-dimensional integrated circuit device fabrication including wafer scale membrane

Applicant:

Globalfoundries U.s. 2 Llc, Hopewell Junction, NY (US);

Inventors:

Douglas C. La Tulipe, Jr., Guilderland, NY (US);

Sampath Purushothaman, Yorktown Heights, NY (US);

James Vichiconti, Peekskill, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:

Yuanmin Cai, Esq.

Primary Examiner:

Selim Ahmed

Int. Cl.
CPC ...
H01L 21/77 (2006.01); H01L 21/322 (2006.01); H01L 21/02 (2006.01); H01L 21/683 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 29/06 (2006.01); C23C 16/40 (2006.01); C23C 16/513 (2006.01); C23C 16/56 (2006.01); H01L 21/18 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3221 (2013.01); C23C 16/402 (2013.01); C23C 16/513 (2013.01); C23C 16/56 (2013.01); H01L 21/02002 (2013.01); H01L 21/187 (2013.01); H01L 21/67063 (2013.01); H01L 21/67069 (2013.01); H01L 21/6835 (2013.01); H01L 21/76251 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 29/06 (2013.01); H01L 2221/68377 (2013.01); H01L 2224/83121 (2013.01); H01L 2225/06513 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01);
Abstract

Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor wafer is etched. The substrate side is located opposite a device layer and has a buried insulating layer and a substrate thickness. The etching removes at least a substantial portion of the crystalline substrate within the area such that the device layer and the buried insulating layer in the area is to conform to a pattern specific topology on an acceptor surface. The donor semiconductor wafer is supported with a supporting structure that allows the donor semiconductor wafer to flexibly conform to the pattern specific topology within at least a portion of the area after the etching to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

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