The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2017
Filed:
Dec. 03, 2014
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Kangguo Cheng, Schenectady, NY (US);
Bruce B. Doris, Slingerlands, NY (US);
Ali Khakifirooz, Los Altos, CA (US);
Douglas C. La Tulipe, Jr., Guilderland, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/772 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78603 (2013.01); H01L 29/0847 (2013.01); H01L 29/495 (2013.01); H01L 29/4908 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66628 (2013.01); H01L 29/772 (2013.01); H01L 29/785 (2013.01); H01L 29/78654 (2013.01);
Abstract
A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.