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For the Inventor, By the Inventor

Kaohsiung, Taiwan

Chin-Liang Chen

This inventor holds 60 USPTO granted patents and 15 published patent applications, primarily in Semiconductor Packaging (CPC class H01L). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Taiwan Semiconductor Manufacturing Co., Ltd., Henghao Technology Co. Limited. Active years: 2014-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chin-Liang Chen. Retrieved from https://idiyas.com/inventor/chin-liang-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 60 

% Patents Active = 86.7

Average Co-Inventor Count = 4.8

ph-index = 6

Forward Citations = 111(Granted Patents)

Forward Citations (Not Self Cited) = 88(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Hsinchu, TW (2014 - 2024)
  • Kaohsiung, TW (2015 - 2024)

Company Filing History:

goldMedal57 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal2 out of 481 
 
Taiwan Semiconductor Manufacturing Co., Ltd.
 patents
bronzeMedal1 out of 27 
 
Henghao Technology Co. Limited
 patents

Years Active: 2014-2026

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Areas of Expertise:
Semiconductor Structure
Circuit Structure
Die Corner Removal
Underfill Crack Suppression
Integrated Fan-Out Package
Lid Attach Process
Thermal Management
Package Structure
Manufacturing Method
Bonding Package Lid
Heat Dissipation
3D Stacking
60 patents (USPTO):Explore Patents
1. 12685236 - Semiconductor device packages and methods of forming the same (2026-07-14),
2. 12660603 - Hybrid cut metal gate to achieve minimum cell pitches, reducing routing and rising the yield (2026-06-16),
3. 12642111 - Package structure (2026-05-26),
4. 12635554 - Integrated circuit packages and methods of forming same (2026-05-19),
5. 12417969 - Semiconductor structure and circuit structure (2025-09-16),
6. 12417968 - Package structure and forming method thereof (2025-09-16),
7. 12412846 - Semiconductor package and methods of fabricating a semiconductor package (2025-09-09),
8. 12347802 - Die corner removal for underfill crack suppression in semiconductor die packaging (2025-07-01),
9. 12165946 - Semiconductor package and manufacturing method thereof (2024-12-10),
10. 12062619 - Semiconductor packages and forming methods thereof (2024-08-13),
11. 12062604 - Semiconductor structure and manufacturing method thereof (2024-08-13),
12. 11972956 - Lid attach process and dispenser head (2024-04-30),
13. 11908835 - Semiconductor structure and manufacturing method thereof (2024-02-20),
14. 11824032 - Die corner removal for underfill crack suppression in semiconductor die packaging (2023-11-21),
15. 11810847 - Package structure and method of fabricating the same (2023-11-07),

Title: Inventor Chin-Liang Chen: Revolutionizing Technology in Kaohsiung

Introduction: Chin-Liang Chen is a pioneering inventor based in Kaohsiung, Taiwan, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Chen's latest patents focus on advancements in renewable energy technologies, artificial intelligence systems, and sustainable manufacturing processes, showcasing his commitment to creating a more sustainable future.

Career Highlights: With a career spanning over two decades, Chin-Liang Chen has established himself as a leading figure in the tech industry, with numerous successful inventions that have significantly impacted various sectors.

Collaborations: Throughout his career, Chen has collaborated with top research institutions, leading companies, and innovative startups to bring his inventions to life, fostering a culture of innovation and collaboration in the industry.

Conclusion: Chin-Liang Chen's relentless pursuit of innovation and his passion for creating cutting-edge technologies continue to inspire the next generation of inventors and shape the future of technology in Kaohsiung and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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