The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2024
Filed:
Jul. 11, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Kuan-Lin Ho, Hsinchu, TW;
Chin-Liang Chen, Kaohsiung, TW;
Jiun-Yi Wu, Taoyuan, TW;
Chi-Yang Yu, Taoyuan, TW;
Yu-Min Liang, Taoyuan, TW;
Wei-Yu Chen, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.