Taiwan Semiconductor Manufacturing Comp. Ltd.

Henghao Technology Co. Limited

Chin-Liang Chen

Kuan-Lin Ho

Chi-Yang Yu

Yu-Min Liang

Yu-Chih Liu

Wei-Ting Lin

Shih-Yen Lin

Jiun-Yi Wu

Wei-Yu Chen

Yu-min Liang

Hai-Ming Chen

Wen-Lin Chen

Jason Shen

Chien-Hsun Lee

Jing Ruei Lu

Chia-Min Lin

Pei-Rong Ni

Chen-Hua Douglas Yu

Kai-Chiang Wu

Jiun Yi Wu

Tsung-Ding Wang

Chun-Cheng Lin

Yen-Ping Wang

Jung Wei Cheng

Hao-Cheng Hou

Jung-Wei Cheng

Chang-Chia Huang

Hsin-Yu Pan

Sheng-Hsiang Chiu

Chien-Kuo Chang

Ting-Chieh Chen

Chi-yang Yu

A package structure and a manufacturing method thereof are provided. The package structure includes an integrated substrate and a package component. The integrated substrate includes a substrate component laterally covered by an insulating encapsulation, a redistribution structure disposed over the substrate component and the insulating encapsulation, first conductive joints coupling the redistribution structure to the substrate component, and a buffer layer disposed on a lowermost dielectric layer of the redistribution structure and extending downwardly to cover an upper portion of each of the first conductive joints. A lower portion of each of the first conductive joints connected to the upper portion is covered by the insulating encapsulation. The package component disposed over and electrically coupled to the redistribution structure includes a semiconductor die laterally covered by an encapsulant.

Package structure and forming method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.

Semiconductor structure and circuit structure

A semiconductor package provided herein includes a package substrate and a semiconductor device. The package substrate includes a redistribution structure, an interconnect structure bonded to the interconnect structure and an insulation material laterally surrounding the interconnect structure, wherein the redistribution structure has a reduced structure and the insulation material fills the reduced structure. The semiconductor device is bonded to the package substrate. In addition, a method of fabricating a semiconductor package is also provided and includes a precut process forming the reduced structure in the redistribution structure of the package substrate.

Semiconductor package and methods of fabricating a semiconductor package

A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Die corner removal for underfill crack suppression in semiconductor die packaging

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Semiconductor package and manufacturing method thereof

A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

Semiconductor packages and forming methods thereof

A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Semiconductor structure and manufacturing method thereof

A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.

Lid attach process and dispenser head

A method of manufacturing a semiconductor structure includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar arid a third conductive pillar are disposed over the substrate. The first conductive pillar comprises a first height, the second conductive pillar comprises a second height, and the third conductive pillar comprises a third height. A first die is disposed over the first conductive pillar. A second die is disposed over the second conductive pillar. A first surface of the first die and a second surface of the second die are at substantially same level.

A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights.

Package structure and method of fabricating the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via.

An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

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Kaohsiung, Taiwan

Chin-Liang Chen