The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2025
Filed:
Aug. 09, 2023
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Wei-Yu Chen, Hsinchu, TW;
Chi-Yang Yu, Zhongli, TW;
Kuan-Lin Ho, Hsinchu, TW;
Chin-Liang Chen, Kaohsiung, TW;
Yu-Min Liang, Zhongli, TW;
Jiun Yi Wu, Zhongli, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Abstract
A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.