Chien-Hsun Lee

Chutung, Taiwan

Chien-Hsun Lee

This inventor holds 141 USPTO granted patents and 46 published patent applications, primarily in Semiconductor Packaging (CPC class H01L25-50). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Taiwan Semiconductor Manufacturing Co., Ltd., Holtek Semiconductor Corp.. Active years: 2008-2026.

USPTO Granted Patents = 141 

% Patents Active = 94.3

Average Co-Inventor Count = 4.3

ph-index = 11

Forward Citations = 2,296(Granted Patents)

Forward Citations (Not Self Cited) = 2,010(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Chu-tung, TW (2015 - 2019)
  • Hsinchu, TW (2008 - 2023)
  • Chu-tung Town, TW (2014 - 2024)
  • Hsin-chu County, TW (2017 - 2024)

Company Filing History:


Years Active: 2008-2026

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Areas of Expertise:
Semiconductor Device
Multi-Die Package
Thermal Stress
Integrated Circuit
Redistribution Layers
Electronic Assembly
Wafer Level Package
Connection Structures
Inductor Structure
Circuit Carrier
Manufacturing Method
Copper Pillars
141 patents (USPTO):Explore Patents

Chien-Hsun Lee: An Innovative Mind with 100 Patents

Chien-Hsun Lee is a prominent inventor and innovator from Chu-tung Town, Taiwan, who has earned a reputation for his exceptional work in the field of integrated circuit packaging. Lee has been awarded a total of 100 patents to date, a testament to his dedication and expertise in his chosen field.

In his latest patents, Lee has developed an innovative package structure that features a buffer layer to reduce thermal stress. This package structure includes a first die and a second die, with the first encapsulant encapsulating both. The buffer layer with lower Young's modulus is disposed between the first and second encapsulants and covers at least a sidewall of the second die.

Lee's integrated circuit packages are also noteworthy, as he has developed an efficient and cost-effective method of forming them. In these packages, a first die is mounted on a first side of a workpiece that includes a second die. A heat dissipation feature may be attached to the second side of the workpiece, followed by the formation of an encapsulant around the workpiece on the package substrate's front side.

Chien-Hsun Lee's incredible achievements in the field of integrated circuit packaging have been recognized by several semiconductor companies. He has worked with Taiwan Semiconductor Manufacturing Company Limited and Holtek Semiconductor Corp. during his career.

Lee has also collaborated with his peers Tsung-Ding Wang and Chen-Hua Yu. Together, they have made contributions in the field of integrated circuit packaging that have advanced the field's techniques and technology.

In conclusion, Chien-Hsun Lee is a trailblazer in the field of integrated circuit packaging, with an impressive portfolio of patents to his name. His innovative solutions have made a significant impact on the industry, and his dedication to his work continues to inspire his peers.

Profile summary based on public USPTO records.
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