logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12482790 B1

PDFFull Text
Date of Patent:
Nov. 25, 2025

Filed:

Apr. 18, 2023

Packages with stacked dies and methods of forming the same

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chien-Hsun Lee, Chu-tung Town, TW;

Tsung-Ding Wang, Tainan, TW;

Mirng-Ji Lii, Sinpu Township, TW;

Chen-Hua Yu, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Shahed Ahmed

Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 21/78 (2013.01); H01L 23/3675 (2013.01); H01L 23/3736 (2013.01); H01L 23/49827 (2013.01); H01L 24/00 (2013.01); H01L 24/97 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Find Patent Forward Citations

Loading…