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For the Inventor, By the Inventor

Hsinchu, Taiwan

Chien-Hsiun Lee

This inventor holds 42 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Packaging. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2006-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chien-Hsiun Lee. Retrieved from https://idiyas.com/inventor/chien-hsiun-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 42 

% Patents Active = 71.4

Average Co-Inventor Count = 3.7

ph-index = 11

Forward Citations = 390(Granted Patents)


Location History:

  • Chu-tung, TW (2014)
  • Hsin-Chu, TW (2006 - 2019)
  • Chu-tung Town, TW (2014 - 2020)

Company Filing History:

goldMedal42 out of 42,810 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2006-2020

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Areas of Expertise:
Interconnect Structures
Flip-Chip Bonding
Wafer-Level Assembly
Package-On-Package
Solder Connections
Stacked-Die Packages
Thermal Management
Molded Structure
Low CTE Substrates
Die Assembly
Solder Ball Protection
Wafer-Level Chip-Scale Packaging
42 patents (USPTO):Explore Patents
1. 10777431 - Post-passivation interconnect structure and method of forming the same (2020-09-15),
2. 10665565 - Package assembly (2020-05-26),
3. 10453815 - Methods and apparatus for solder connections (2019-10-22),
4. 10192848 - Package assembly (2019-01-29),
5. 10163877 - System in package process flow (2018-12-25),
6. 9905520 - Solder ball protection structure with thick polymer layer (2018-02-27),
7. 9780064 - Method of forming package assembly (2017-10-03),
8. 9768105 - Rigid interconnect structures in package-on-package assemblies (2017-09-19),
9. 9515036 - Methods and apparatus for solder connections (2016-12-06),
10. 9449941 - Connecting function chips to a package to form package-on-package (2016-09-20),
11. 9240387 - Wafer-level chip scale package with re-workable underfill (2016-01-19),
12. 9105552 - Package on package devices and methods of packaging semiconductor dies (2015-08-11),
13. 9059109 - Package assembly and method of forming the same (2015-06-16),
14. 8987605 - Formation of connectors without UBM (2015-03-24),
15. 8932906 - Through silicon via bonding structure (2015-01-13),

Title: Innovator Spotlight: Chien-Hsiun Lee - Pioneering Semiconductor Technology

Introduction: Chien-Hsiun Lee, a renowned inventor in the field of semiconductor technology, has made significant contributions in Hsin-Chu, Taiwan. With an impressive portfolio of 42 patents, Lee's groundbreaking work continues to shape the future of integrated chip structures.

Latest Patents: Lee's recent patents showcase his expertise in semiconductor device design. The "Post-passivation interconnect structure and method of forming the same" patent highlights his innovative approach to enhancing semiconductor performance. Similarly, the "Package assembly" patent underscores his focus on integrated chip structures, demonstrating his impact on the industry.

Career Highlights: Lee's career includes notable stints at Taiwan Semiconductor Manufacturing Company Ltd. and Taiwan Semiconductor Manufacturing Co., Ltd. His strategic roles in these leading semiconductor companies have solidified his reputation as a trailblazer in the field, driving innovation and technological advancements.

Collaborations: Throughout his career, Lee has collaborated with esteemed professionals like Mirng-Ji Lii and Tsung-Ding Wang. These collaborations have resulted in the development of cutting-edge technologies and the expansion of knowledge within the semiconductor industry.

Conclusion: Chien-Hsiun Lee's dedication to innovation and relentless pursuit of excellence have established him as a key figure in semiconductor technology. His numerous patents, successful career at prominent companies, and collaborative efforts underscore his contributions to the field. Lee's groundbreaking work continues to inspire future generations of inventors and shape the landscape of semiconductor technology globally.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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