The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Sep. 23, 2019
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 21/566 (2013.01); H01L 23/3114 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 23/525 (2013.01); H01L 23/564 (2013.01); H01L 24/11 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/0347 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/1191 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13005 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2924/181 (2013.01);
Abstract
A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.