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For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

Ajit P Paranjpe

This inventor holds 55 USPTO granted patents and 14 published patent applications and 1 EPO patent, primarily in Wafer Processing (CPC class H01L). Top assignees: Texas Instruments Corporation, Cvc Products, Inc., Veeco Instruments Inc.. Active years: 1993-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ajit P Paranjpe. Retrieved from https://idiyas.com/inventor/ajit-p-paranjpe

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 55 

% Patents Active = 72.7

 

Average Co-Inventor Count = 2.0

ph-index = 24

Forward Citations = 1,691(Granted Patents)

Forward Citations (Not Self Cited) = 1,683(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Dallas, TX (US) (1993 - 1998)
  • Plano, TX (US) (1995 - 2002)
  • Sunnyvale, CA (US) (1998 - 2005)
  • Fremont, CA (US) (2004 - 2010)
  • Basking Ridge, NJ (US) (2013 - 2021)

Company Filing History:

goldMedal23 out of 29,869 
 
Texas Instruments Corporation
 patents
silverMedal11 out of 46 
 
Cvc Products, Inc.
 patents
bronzeMedal11 out of 311 
 
Veeco Instruments Inc.
 patents
4. 5 out of 14,433 
 
Applied Materials, Inc.
 patents
5. 2 out of 2 
 
Veeco-Cvc, Inc.
 patents
6. 1 out of 33 
 
Directed Electronics Inc.
 patents
7. 2 out of 834,453 
Other
 patents

Years Active: 1993-2024

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Areas of Expertise:
Wafer Processing
Thin Film Deposition
Microelectronic Interconnects
Chemical Vapor Deposition
Physical Vapor Deposition
Tantalum-Based Films
Silicon Fill
STT-RAM Structures
Carrier Cleaning
Light-Based Debonding
Crystalline-Nitride Devices
55 patents (USPTO):Explore Patents
1. 12104242 - Deposition system with integrated carrier cleaning modules (2024-10-01),
2. 10985046 - Micro-LED transfer methods using light-based debonding (2021-04-20),
3. 10167554 - Wafer processing with carrier extension (2019-01-01),
4. 9978934 - Ion beam etching of STT-RAM structures (2018-05-22),
5. 9938621 - Methods of wafer processing with carrier extension (2018-04-10),
6. 9761671 - Engineered substrates for use in crystalline-nitride based devices (2017-09-12),
7. 9356188 - Tensile separation of a semiconducting stack (2016-05-31),
8. 9230846 - Multi-wafer rotating disc reactor with inertial planetary drive (2016-01-05),
9. 8562746 - Sectional wafer carrier (2013-10-22),
10. 7713881 - Process sequence for doped silicon fill of deep trenches (2010-05-11),
11. 7446366 - Process sequence for doped silicon fill of deep trenches (2008-11-04),
12. 7393561 - Method and apparatus for layer by layer deposition of thin films (2008-07-01),
13. 7354848 - Poly-silicon-germanium gate stack and method for forming the same (2008-04-08),
14. 7109097 - Process sequence for doped silicon fill of deep trenches (2006-09-19),
15. 7037574 - Atomic layer deposition for fabricating thin films (2006-05-02),

Title: The Innovative Journey of Ajit P Paranjpe

Introduction: Ajit P Paranjpe is a pioneering inventor based in Sunnyvale, California, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Ajit P Paranjpe holds several patents in various technological domains, showcasing his continuous dedication to pushing the boundaries of innovation.

Career Highlights: With a career spanning over two decades, Ajit P Paranjpe has worked with renowned tech companies, leading research institutions, and universities, solidifying his reputation as a visionary in the tech industry.

Collaborations: Throughout his career, Ajit P Paranjpe has collaborated with top-notch engineers, scientists, and researchers, fostering a culture of innovation and excellence in all his projects.

Conclusion: Ajit P Paranjpe's relentless pursuit of innovation and his remarkable contributions to the tech industry make him a standout figure in the world of inventors and innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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