The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2013

Filed:

Dec. 15, 2010
Applicants:

Alexander I. Gurary, Bridgewater, NJ (US);

Joseph Arthur Kraus, Hamilton, NJ (US);

Ajit Paranjpe, Basking Ridge, NJ (US);

William E. Quinn, Whitehouse Station, NJ (US);

David Albert Crewe, Basking Ridge, NJ (US);

Inventors:

Alexander I. Gurary, Bridgewater, NJ (US);

Joseph Arthur Kraus, Hamilton, NJ (US);

Ajit Paranjpe, Basking Ridge, NJ (US);

William E. Quinn, Whitehouse Station, NJ (US);

David Albert Crewe, Basking Ridge, NJ (US);

Assignee:

Veeco Instruments Inc., Plainview, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C23C 16/00 (2006.01); C23F 1/00 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structure for a chemical vapor deposition reactor includes a support element defining oppositely-facing substantially planar upper and lower surfaces and a vertical rotational axis substantially perpendicular to the upper and lower surfaces, and a plurality of carrier sections releasably engaged with the support element. Each carrier section can include oppositely-facing substantially planar top and bottom surfaces and at least one aperture extending between the top and bottom surfaces. The carrier sections can be disposed on the support element with the bottom surfaces of the carrier sections facing toward the upper surface of the support element, so that wafers can be held in the apertures of the carrier sections with one surface of each wafer confronting the support element and an opposite surface exposed at the top surface of the carrier sections.


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