Texas Instruments Corporation

Veeco Instruments Inc.

Cvc Products, Inc.

Applied Materials, Inc.

Other

Veeco-cvc, Inc.

Directed Electronics Inc.

Ajit P Paranjpe

Mehrdad M Moslehi

Randhir S Bubber

Lino A Velo

Cecil J Davis

Thomas R Omstead

Sanjay Gopinath

David R Campbell, Sr

Somnath S Nag

David M Leet

Boris Relja

Alexander I Gurary

Robert T Matthews

Walter Marvin Duncan

Craig Metzner

Eric Armour

Bojan Mitrovic

Dorian Heimanson

Steven A Henck

Steve S Huang

Jimmy W Hosch

Pushkar Prabhakar Apte

Phillip Chapados, Jr

Peter V Schwartz

Jacques Kools

Kang Song

Guanghua Wei

William E Quinn

Ming Mao

Thomas J Aton

Yong Jin Lee

Francis Gabriel Celii

Boris L Druz

Joe H Lamb

Habib N Najm

Christopher J Morath

Mandar Deshpande

Douglas L Mahlum

Adrian Celaru

Todd A Luse

Joseph Arthur Kraus

Katrina Rook

Larry A Taylor

Kangzhan Zhang

Dwain R Jakubik

Jia Lee

Joseph Scandariato

Guihua Shang

Qingfu Tang

Zeming Liu

David Albert Crewe

Christopher J Mann

Narasimhan Srinivasan

Eric A Armour

A chemical vapor deposition system for semiconductor wafer production is disclosed. The system includes a process cluster coupled to a first end of a transfer chamber. The process cluster is maintained at a pressure that is lower than atmospheric pressure. The process cluster is also configured to apply epitaxial layers on one or more wafers loaded onto a wafer carrier. The system also includes an automatic factory interface coupled to a second end of the transfer chamber. The automatic factory interface is maintained at atmospheric pressure. The system includes one or more wafer carrier cleaning modules coupled to the automatic factory interface and configured to clean one or more of the wafer carriers without removing the wafer carriers from the chemical vapor deposition system.

Deposition system with integrated carrier cleaning modules

Transfer methods disclosed herein include transferring micro-LEDs from a first carrier to a second carrier. The methods include bonding the micro-LEDs to the first carrier using a first releasable bonding layer that releases when exposed to actinic light. The micro-LEDs are then secured to a second carrier. The first bonding layer is then irradiated through the first releasable bonding layer through the first carrier with the actinic light to release the micro-LEDs from the first carrier. The second carrier can be a display backplane having bonding pads and the micro-LEDs can be secured to the bonding pads.

Micro-LED transfer methods using light-based debonding

Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.

Wafer processing with carrier extension

This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.

Ion beam etching of STT-RAM structures

Methods are provided for treating wafers using a wafer carrier rotated about an axis. The wafer carrier is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.

Methods of wafer processing with carrier extension

A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.

Engineered substrates for use in crystalline-nitride based devices

A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.

Tensile separation of a semiconducting stack

Wafer carriers and methods for moving wafers in a reactor. The wafer carrier may include a platen with a plurality of compartments and a plurality of wafer platforms. The platen is configured to rotate about a first axis. Each of the wafer platforms is associated with one of the compartments and is configured to rotate about a respective second axis relative to the respective compartment. The platen and the wafer platforms rotate with different angular velocities to create planetary motion therebetween. The method may include rotating a platen about a first axis of rotation. The method further includes rotating each of a plurality of wafer platforms carried on the platen and carrying the wafers about a respective second axis of rotation and with a different angular velocity than the platen to create planetary motion therebetween.

Multi-wafer rotating disc reactor with inertial planetary drive

A structure for a chemical vapor deposition reactor includes a support element defining oppositely-facing substantially planar upper and lower surfaces and a vertical rotational axis substantially perpendicular to the upper and lower surfaces, and a plurality of carrier sections releasably engaged with the support element. Each carrier section can include oppositely-facing substantially planar top and bottom surfaces and at least one aperture extending between the top and bottom surfaces. The carrier sections can be disposed on the support element with the bottom surfaces of the carrier sections facing toward the upper surface of the support element, so that wafers can be held in the apertures of the carrier sections with one surface of each wafer confronting the support element and an opposite surface exposed at the top surface of the carrier sections.

Sectional wafer carrier

A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Process sequence for doped silicon fill of deep trenches

A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

A method of increasing ALP briefly, a preferred embodiment of the present invention includes a method of increasing ALP throughput by continuously modulating gas flow in a reactor to achieve layer by layer growth on a wafer. A first reactant is introduced with a percentage of a carrier gas. After a first time interval, the first reactant flow is reduced while the carrier gas flow is increased so as to maintain an approximately constant total gas flow. When the first reactant flow reaches a minimal, predetermined amount, a second reactant flow is initiated and increased while the carrier gas flow is decreased so as to continue a constant total gas flow. The method alternatively includes introducing a substance that enhances reactant adsorption and chemisorption, either as a first applied gas that reacts with the surface or as an added ligand to the reactant. Still further alternatives include a periodic rapid thermo anneal for improving film properties, parallel wafer processing and a reactant reservoir.

Method and apparatus for layer by layer deposition of thin films

A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin &#x3b1;-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second &#x3b1;-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

Poly-silicon-germanium gate stack and method for forming the same

An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (R&#x2dc;2 &#x212b;), pure (impurities&#x3c;1 at. %), AlOfilms with improved breakdown strength (9&#x2013;10 MV/cm) with a commercially feasible throughput.

Atomic layer deposition for fabricating thin films

Growing community of inventors

Sunnyvale, CA, United States of America

Ajit P Paranjpe