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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Easic Corporation


USPTO Granted Patents = 35

% Expired Patents = 8.6



Forward Citations = 5,474

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44 inventors (with patents filed for the assignee):

goldMedal Zvi Or-Bach (21 out of 518 patents)

silverMedal Ze'ev Wurman (6 out of 16 patents)

bronzeMedal Alexander Andreev (5 out of 112 patents)

4.  Adam E Levinthal (5 out of 19 patents)

5.  Richard Zeman (5 out of 5 patents)

6.  Sergey Vladimirovich Gribok (4 out of 33 patents)

7.  Hui Hui Ngu (4 out of 4 patents)

8.  Romeo Iacobut (4 out of 4 patents)

9.  Adrian Apostol (4 out of 5 patents)

10.  Herman Henry Schmit (3 out of 141 patents)

11.  Jonathan C Park (3 out of 16 patents)

12.  Ranko L Scepanovic (3 out of 164 patents)

13.  Soon Chieh Lim (3 out of 6 patents)

14.  Petrica Avram (3 out of 3 patents)

15.  Laurance Cooke (3 out of 3 patents)


Core Competencies:
Structured ASIC
Programmable Cell Array
Multi-Port Memory
Clock Network
Transistor Chains
Dynamic Phase Alignment
Customizable Logic
MEMS Switching
High-Performance Logic
28 NM CMOS
Integrated Circuits
Semiconductor Device

35 patents:

1. RE46474 - Multiple write during simultaneous memory access of a multi-port memory device (2017-07-10),
2. 9704874 - ROM segmented bitline circuit (2017-07-11),
3. 9024657 - Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller (2015-05-05),
4. 8957398 - Via-configurable high-performance logic block involving transistor chains (2015-02-17),
5. 8848479 - Multiple write during simultaneous memory access of a multi-port memory device (2014-09-30),
6. 8735857 - Via-configurable high-performance logic block architecture (2014-05-27),
7. 8677306 - Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC (2014-03-18),
8. 8629548 - Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node (2014-01-14),
9. 8504865 - Dynamic phase alignment (2013-08-06),
10. 8436700 - MEMS-based switching (2013-05-07),
11. 8339844 - Programmable vias for structured ASICs (2012-12-25),
12. 8040739 - Configurable write policy in a memory system (2011-10-18),
13. 7759971 - Single via structured IC device (2010-07-20),
14. 7689960 - Programmable via modeling (2010-03-30),
15. 7550996 - Structured integrated circuit device (2009-06-23),
Company Overview
Easic Corporation, headquartered in Santa Clara, California, specializes in advanced semiconductor solutions and integrated circuit design. The company focuses on providing innovative technologies that enhance performance and efficiency in various applications, including telecommunications, consumer electronics, and automotive systems. Easic's expertise lies in developing customizable hardware solutions that cater to the evolving needs of industries, positioning itself as a key player in the semiconductor landscape.
Profile summary synthesized from public USPTO records and patent filings.

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USPTO Data Jan 1 1976 - Oct 13 2026

Easic Corporation USPTO Patent Assignee Logo
35 Patents

#101 in Santa Clara, CA

#2,308 in California

#9,749 in US

#19,168 in the World

Santa Clara, CA (US)
Santa Clara, CA, United States of America

Easic Corporation

Forward Citations = 5,474

44 inventors:

goldMedal Zvi Or-Bach (21 out of 518 patents)

silverMedal Ze'ev Wurman (6 out of 16 patents)

bronzeMedal Alexander Andreev (5 out of 112 patents)

4.  Adam E Levinthal (5 out of 19 patents)

5.  Richard Zeman (5 out of 5 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Easic Corporation. Retrieved from https://idiyas.com/company/easic

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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