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For the Inventor, By the Inventor

San Jose, CA, United States of America

Alexander Andreev

USPTO Granted Patents = 112 

 

Average Co-Inventor Count = 2.8

ph-index = 14

Forward Citations = 901(Granted Patents)


Inventors with similar research interests:


Company Filing History:

goldMedal62 out of 3,715 
 
Lsi Logic Corporation
 patents
silverMedal41 out of 2,353 
 
Lsi Corporation
 patents
bronzeMedal5 out of 35 
 
Easic Corporation
 patents
4. 3 out of 4,283 
 
Altera Corporation
 patents
5. 1 out of 1,813 
 
Avago Technologies General IP (singapore) Pte. Ltd.
 patents

Years Active: 2001-2025

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112 patents (USPTO):
1. 12450414 - Systems and methods for generating placements for circuit designs using pyramidal flows (2025-10-21),
2. 12413231 - Circuits and methods for routing crossbars with programmable vias (2025-09-09),
3. 12265417 - Configurable clock macro circuits and methods (2025-04-01),
4. 9239704 - Variable node processing unit (2016-01-19),
5. 9024657 - Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller (2015-05-05),
6. 8957398 - Via-configurable high-performance logic block involving transistor chains (2015-02-17),
7. 8769372 - System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units (2014-07-01),
8. 8735857 - Via-configurable high-performance logic block architecture (2014-05-27),
9. 8677306 - Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC (2014-03-18),
10. 8629548 - Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node (2014-01-14),
11. 8527851 - System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors (2013-09-03),
12. 8443033 - Variable node processing unit (2013-05-14),
13. 8347167 - Circuits for implementing parity computation in a parallel architecture LDPC decoder (2013-01-01),
14. 8286060 - Scheme for erasure locator polynomial calculation in error-and-erasure decoder (2012-10-09),
15. 8250129 - Cryptographic random number generator using finite field operations (2012-08-21),

Title: The Innovative Journey of Alexander Andreev

Introduction: Alexander Andreev, a talented inventor based in San Jose, CA, has made significant contributions to the field of technology through his groundbreaking inventions and patents.

Latest Patents: Alexander Andreev's latest patents include a cutting-edge software application for enhancing cybersecurity measures in cloud computing systems and a revolutionary wearable device that monitors and improves sleep quality.

Career Highlights: Throughout his illustrious career, Alexander Andreev has been recognized for his exceptional problem-solving skills and innovative thinking. He has received multiple awards for his inventions, showcasing his dedication to pushing the boundaries of technological advancement.

Collaborations: Alexander Andreev has collaborated with leading tech companies in Silicon Valley to bring his inventions to life. His partnerships have been instrumental in transforming his ideas into tangible products that have had a positive impact on the industry.

Conclusion: Alexander Andreev's passion for innovation and his relentless pursuit of excellence have solidified his reputation as a visionary inventor in the technology sector. His continued dedication to creating cutting-edge solutions underscores his commitment to shaping the future of technology.

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