Lsi Logic Corporation

Lsi Corporation

Easic Corporation

Altera Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Alexander Andreev

Ranko L Scepanovic

Anatoli Aleksandrovich Bolotov

Andrey Nikitin

Igor A Vikhliantsev

Ivan Pavisic

Sergey Vladimirovich Gribok

Vojislav Vukovic

Pavel Anatolyevich Panteleev

Ilya Vladimirovich Neznanov

Elyar Eldarovich Gasanov

Pedja Raspopovic

Anatoli A Bolotov

Sergei B Gashkov

Oleg N Izyumin

Mikhail I Grinchuk

Lav D Ivanovic

Aiguo Lu

Pavel Aleksandrovich Aliseychik

Sergey Y Gribok

Egor A Andreev

Chee-Wei Kung

Phey-Chuin Tan

Alexander Rusakov

Sergej B Gashkov

Atul Maheshwari

Eng Huat Lee

Nikola Radovanovic

Andrey V Nikishin

Sergey B Gashkov

Seow-Sung Lee

David Parkhouse

Alexander Yakhontov

Massimo Verita

Wayson Lowe

Ban Wong

Choon-Hun Choo

Marian Serbian

Andrei Nikishin

Vojislav Vukovie

Alexander Yahontov

Vojislav Vokovic

Mikhail Udovikhin

Chong-Teik Lim

Oleg B Sedelev

Oleg Izyumin

Ranko Scepanovic

Sergey Gribok

Igor Vikhliantsev

A circuit design system is configured to generate a circuit design for an integrated circuit. The circuit design system includes a placement tool configured to generate a graph comprising flows between objects in a first level of a pyramid and targets in the first level. The placement tool generates clusters of objects in a second level of the pyramid in each of the objects in the first level. The objects in the first and the second levels comprise circuit blocks in the circuit design. The placement tool generates clusters of targets in the second level of the pyramid in each of the targets in the first level. The targets in the first and the second levels include subregions of the integrated circuit. The placement tool generates flows from the objects in the second level to the targets in the second level for a placement of the circuit blocks.

Systems and methods for generating placements for circuit designs using pyramidal flows

An integrated circuit includes first and second routing crossbars. The second routing crossbar includes first conductors routed in a first direction in a first conductive layer and second conductors routed in a second direction that is perpendicular to the first direction in a second conductive layer. A first subset of the first conductors is coupled to the first routing crossbar. The first subset of the first conductors is coupled to a second subset of the first conductors through a first subset of the second conductors that is coupled to the first and second subsets of the first conductors through first vias. The second subset of the first conductors is coupled to a second subset of the second conductors to through second vias. At least one of the first conductors is decoupled from another one of the first conductors by third vias.

Circuits and methods for routing crossbars with programmable vias

An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.

Configurable clock macro circuits and methods

A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value.

Variable node processing unit

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller

A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.

Via-configurable high-performance logic block involving transistor chains

A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the method includes: (1) representing the turbo decoding system as a resource diagram rectangle, (2) representing the code blocks as code block rectangles, (3) mapping the code block rectangles into the resource diagram rectangle and (4) assigning the code blocks to the constituent decoding units based on the mapping.

System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units

A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.

Via-configurable high-performance logic block architecture

A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric comprising network agents in a scalable novel configuration, with the network-aware IO having a plurality of blocks connected in series in a plurality of paths in the fabric leading to and from the microprocessor and memory and/or logic, the blocks acting as intelligent network agents under processor control to determine what state they can assume, whether to pass a data signal or not along these paths, comprising open loops and closed loops running to and from the microprocessor and memory and/or logic, primarily for testing and determining the state of the memory and logic. In another embodiment a JTAG controller may receive JTAG test commands from an external testing apparatus and set up to communicate along the fabric.

Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC

A clock architecture for a Structured ASIC chip, manufactured using a CMOS process is shown. A via-configurable logic block (VCLB) architecture in the Structured ASIC has a core region containing memory and logic cells arranged in columns that are supplied by a clock network having a global clock network tree and a low-level clock mesh to distribute the global clock signal in a repeating pattern. The clock mesh has a fishbone configuration in outline and allows for scalable expansion of the clock network. In one embodiment 36 global clocks may be provided to the Structured ASIC, with four clocks per logic cell. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node, having several metal layers but preferably is programmable on a single via layer.

Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node

The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.&#x2014;unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.

System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors

A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.

A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a 'compute' logic block for computing a parity message (with sign) for application to related bit nodes and a 'compute' logic block for updating the data stored in the memory logic block for a next iteration of the LDPC decoder.

Circuits for implementing parity computation in a parallel architecture LDPC decoder

A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Scheme for erasure locator polynomial calculation in error-and-erasure decoder

An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.

Cryptographic random number generator using finite field operations

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San Jose, CA, United States of America

Alexander Andreev