The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Oct. 11, 2012
Easic Corporation, Santa Clara, CA (US);
Alexander Andreev, San Jose, CA (US);
Ranko L. Scepanovic, Saratoga, CA (US);
Ivan Pavisic, San Jose, CA (US);
Alexander Yahontov, Moscow Region, RU;
Mikhail Udovikhin, Moscow Region, RU;
Igor Vikhliantsev, San Jose, CA (US);
Chong-Teik Lim, Penang, MY;
Seow-Sung Lee, Penang, MY;
Chee-Wei Kung, Penang, MY;
eASIC Corporation, Santa Clara, CA (US);
Abstract
A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.