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San Jose, CA, United States of America

Ivan Pavisic

USPTO Granted Patents = 55

EPO Patents = 1

Average Co-Inventor Count = 3.4

ph-index = 16

Forward Citations = 1,397(Granted Patents)

Forward Citations (Not Self Cited) = 1,379(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Cupertino, CA (US) (1998 - 2005)
San Jose, CA (US) (2001 - 2015)

Company Filing History:

45 out of 3,715

Lsi Logic Corporation

Lsi Corporation

Lsi Logig Corporation

Easic Corporation

Years Active: 1998-2015

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Areas of Expertise:

Integrated Circuit Design

Signal Delay Skew

Clock Tree Synthesis

RRAM Configuration

Buffer Insertion

Timing Optimization

Physical Design Automation

Wire Routing Optimization

Cell Placement

Congestion Removal

Memory Tiling Architecture

Density Driven Layout

55 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9024657 - Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller (2015-05-05),

2. 8516425 - Method and computer program for generating grounded shielding wires for signal wiring (2013-08-20),

3. 8239813 - Method and apparatus for balancing signal delay skew (2012-08-07),

4. 7996804 - Signal delay skew reduction system (2011-08-09),

5. 7818703 - Density driven layout for RRAM configuration module (2010-10-19),

6. 7667494 - Methods and apparatus for fast unbalanced pipeline architecture (2010-02-23),

7. 7546505 - Built in self test transport controller architecture (2009-06-09),

8. 7356785 - Optimizing IC clock structures by minimizing clock uncertainty (2008-04-08),

9. 7334204 - System for avoiding false path pessimism in estimating net delay for an integrated circuit design (2008-02-19),

10. 7246337 - Density driven layout for RRAM configuration module (2007-07-17),

11. 7243324 - Method of buffer insertion to achieve pin specific delays (2007-07-10),

12. 7207026 - Memory tiling architecture (2007-04-17),

13. 7194717 - Compact custom layout for RRAM column controller (2007-03-20),

14. 7096442 - Optimizing IC clock structures by minimizing clock uncertainty (2006-08-22),

15. 7093228 - Method and system for classifying an integrated circuit for optical proximity correction (2006-08-15),

Title: Inventor Ivan Pavisic - Revolutionizing Technology in San Jose

Introduction: Ivan Pavisic is a visionary inventor based in San Jose, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Ivan Pavisic holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his commitment to pushing the boundaries of technological advancement.

Career Highlights: With a career spanning over two decades, Ivan Pavisic has worked with leading tech companies, spearheading projects that have revolutionized industries and improved the way we interact with technology on a daily basis.

Collaborations: Throughout his career, Ivan Pavisic has collaborated with top researchers, engineers, and developers, fostering a culture of innovation and creativity that has led to the development of cutting-edge technologies.

Conclusion: Ivan Pavisic's relentless pursuit of innovation and his passion for pushing the limits of technology make him a true pioneer in the field of inventions, with a lasting impact on the world of technology.

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