Lsi Logic Corporation

Lsi Corporation

Easic Corporation

Lsi Logig Corporation

Ivan Pavisic

Ranko L Scepanovic

Aiguo Lu

Alexander E Andreev

Alexander Andreev

Elyar Eldarovich Gasanov

Andrej A Zolotykh

Pedja Raspopovic

James S Koford

Igor A Vikhliantsev

Sandeep Bhutani

Anatoli Aleksandrovich Bolotov

Andrey Nikitin

Cheng-Gang Kong

Alexandre Andreev

Hui-Yin Seto

Ilya Viktorovich Lyalin

Nikola Radovanovic

Igor V Kucherenko

William Lau

Andrej Zolotykih

Edwin R Jones

Lav D Ivanovic

Dusan Petranovic

Sergey Vladimirovich Gribok

Vojislav Vukovic

Weiqing Guo

Anatoli A Bolotov

Chee-Wei Kung

Egor A Andreev

Alexander Yahontov

Mikhail Udovikhin

Chong-Teik Lim

Seow-Sung Lee

Robert Stenberg

Andrej A Zolotykj

Aiquo Lu

Alexandre E Andreev

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller

A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Method and computer program for generating grounded shielding wires for signal wiring

A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

Method and apparatus for balancing signal delay skew

A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Signal delay skew reduction system

A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.

Density driven layout for RRAM configuration module

Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.

Methods and apparatus for fast unbalanced pipeline architecture

A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.

Built in self test transport controller architecture

A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.

Optimizing IC clock structures by minimizing clock uncertainty

A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.

System for avoiding false path pessimism in estimating net delay for an integrated circuit design

A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.

Method of buffer insertion to achieve pin specific delays

A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.

Memory tiling architecture

The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access. Then, positions for the data pins of the top module (and at least one control pin, if applicable) of the top module are assigned in the top module. The instances are arranged within the top module. Signal routing for the instances and the top module are implemented. Power routing is performed for the instances and the top module.

Compact custom layout for RRAM column controller

Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined characteristic along the first path. A second path from the launching cell toward the clock source is back-traced to a common one of the marked cells having the predetermined characteristic. Clock uncertainty is calculated based on the portion of the first path from the common marked cell having the predetermined characteristic to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.

A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes dividing the IC chip into a plurality of local task regions, identifying congruent local task regions, classifying congruent local task regions into corresponding groups, and performing OPC for each group of congruent local task regions. By identifying and grouping congruent local task regions in the IC chip, according to the method and system disclosed herein, only one OPC procedure (e.g., evaluation and correction) needs to be performed per group of congruent local task regions. The amount of data to be evaluated and the number of corrections performed is greatly reduced because OPC is not performed on repetitive portions of the IC chip design, thereby resulting in significant savings in computing resources and time.

Growing community of inventors

San Jose, CA, United States of America

Ivan Pavisic