The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2008
Filed:
Dec. 29, 2005
Weiqing Guo, Fremont, CA (US);
Sandeep Bhutani, Pleasanton, CA (US);
Ivan Pavisic, San Jose, CA (US);
Weiqing Guo, Fremont, CA (US);
Sandeep Bhutani, Pleasanton, CA (US);
Ivan Pavisic, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.