The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Sep. 22, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alexander Rusakov, Moscow, RU;

Alexander Andreev, San Jose, CA (US);

Eng Huat Lee, Bayan Lepas, MY;

Andrei Nikishin, Moscow, RU;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G06F 30/327 (2020.01); H01L 23/538 (2006.01); H01L 27/02 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 30/327 (2020.01); H01L 23/5384 (2013.01); H01L 27/0207 (2013.01); H03K 19/018585 (2013.01);
Abstract

An integrated circuit includes a clock macro circuit. The clock macro circuit includes first, second, and third latch circuits and a multiplexer circuit. The first latch circuit is coupled to the second latch circuit. The multiplexer circuit is coupled to the second and third latch circuits. The clock macro circuit includes programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit. Programming the programmable vias causes the clock macro circuit to function as a selected type of clock circuit.


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