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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Sergey Vladimirovich Gribok

This inventor holds 33 USPTO granted patents and 10 published patent applications and 1 EPO patent, primarily in Programmable Logic Design. Top assignees: Intel Corporation, Lsi Corporation, Easic Corporation. Active years: 2007-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sergey Vladimirovich Gribok. Retrieved from https://idiyas.com/inventor/sergey-vladimirovich-gribok

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33 

% Patents Active = 54.5

 

Average Co-Inventor Count = 2.9

ph-index = 5

Forward Citations = 96(Granted Patents)


Location History:

  • San Jose, CA (US) (2010 - 2016)
  • Santa Clara, CA (US) (2007 - 2023)

Company Filing History:

goldMedal14 out of 56,365 
 
Intel Corporation
 patents
silverMedal11 out of 2,353 
 
Lsi Corporation
 patents
bronzeMedal4 out of 35 
 
Easic Corporation
 patents
4. 2 out of 4,334 
 
Altera Corporation
 patents
5. 1 out of 1,813 
 
Avago Technologies General IP (Singapore) Pte. Ltd.
 patents
6. 1 out of 3,715 
 
Lsi Logic Corporation
 patents

Years Active: 2007-2026

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Areas of Expertise:
Combinational Circuits
Network-On-Chip
Multiplier Regularization
Field Programmable Gate Array
Arithmetic Densities
RAM-Based Shift Register
Cryptographic Random Number Generator
Pipelined Analog To Digital
Low Complexity LDPC
RRAM Memory
Master Controller Architecture
MEMS-Based Switching
33 patents (USPTO):Explore Patents
1. 12743119 - Power savings by register insertion in large combinational circuits (2026-09-22),
2. 11556692 - High performance regularized network-on-chip architecture (2023-01-17),
3. 11467804 - Geometric synthesis (2022-10-11),
4. 11436399 - Method and apparatus for performing multiplier regularization (2022-09-06),
5. 11334318 - Prefix network-directed addition (2022-05-17),
6. 11210063 - Machine learning training architecture for programmable devices (2021-12-28),
7. 11080019 - Method and apparatus for performing synthesis for field programmable gate array embedded feature placement (2021-08-03),
8. 11016733 - Continuous carry-chain packing (2021-05-25),
9. 10922471 - High performance regularized network-on-chip architecture (2021-02-16),
10. 10871946 - Methods for using a multiplier to support multiple sub-multiplication operations (2020-12-22),
11. 10867090 - Method and apparatus for implementing an application aware system on a programmable logic device (2020-12-15),
12. 10790829 - Logic circuits with simultaneous dual function capability (2020-09-29),
13. 10732932 - Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension (2020-08-04),
14. 10715144 - Logic circuits with augmented arithmetic densities (2020-07-14),
15. 10223488 - Method and apparatus for improving system operation by replacing components for performing division during design compilation (2019-03-05),

Title: Sergey Vladimirovich Gribok: Pioneering Inventor from Santa Clara

Introduction: Sergey Vladimirovich Gribok is a renowned inventor based in Santa Clara, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Sergey Vladimirovich Gribok holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his expertise in cutting-edge technologies.

Career Highlights: With a career spanning over two decades, Sergey Vladimirovich Gribok has worked with leading tech companies, spearheading projects that have revolutionized the industry.

Collaborations: Throughout his career, Sergey Vladimirovich Gribok has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and excellence in all his projects.

Conclusion: Sergey Vladimirovich Gribok's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and entrepreneurs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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