The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Mar. 18, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gregg William Baeckler, San Jose, CA (US);

Martin Langhammer, Alderbury, GB;

Sergey Gribok, Santa Clara, CA (US);

Scott J. Weber, Piedmont, CA (US);

Gregory Steinke, Saratoga, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/327 (2020.01); G06F 9/445 (2018.01); G06F 1/03 (2006.01); G06F 30/34 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 1/03 (2013.01); G06F 9/44505 (2013.01); G06F 30/34 (2020.01);
Abstract

A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.


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