The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Sep. 30, 2022
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Martin Langhammer, Alderbury, GB;

Gregg William Baeckler, San Jose, CA (US);

Sergey Vladimirovich Gribok, Santa Clara, CA (US);

Mahesh A. Iyer, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/06 (2006.01); G06F 1/32 (2019.01); G06F 1/3237 (2019.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/06 (2013.01); G06F 1/3237 (2013.01); H03K 19/0016 (2013.01); G06F 1/32 (2013.01);
Abstract

Systems and methods of the present disclosure provide techniques for reducing power consumption of a large combinational circuit using register insertion. In particular, a large circuit may be analyzed to determine the amount of signal switching at various logical points (e.g., stages in the computation) of the circuit. A clock sequence with many pulses in the period of a clock that runs the large combinatorial circuit may be generated. To balance the amount of signal switching at various logical points in the circuit, registers may be inserted at certain points in the large circuit with the clock pulses of the clock sequence assigned to the registers that may not have a constant frequency or may be phase shifted versions of the main clock.


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