For the Inventor, By the Inventor

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San Jose, CA, United States of America

D2s, Inc.

USPTO Granted Patents = 137

% Expired Patents = 12.4

EPO Patents = 3

Trademarks = 3

Forward Citations = 863

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40 inventors (with patents filed for the assignee):

Akira Fujimura (117 out of 141 patents)

Harold Robert Zable (26 out of 28 patents)

Nagesh Shirali (23 out of 23 patents)

4. Kazuyuki Hagiwara (15 out of 15 patents)

5. Michael Tucker (15 out of 15 patents)

6. P Jeffrey Ungar (14 out of 40 patents)

7. Donald Oriordan (13 out of 13 patents)

8. Ryan Pearman (12 out of 13 patents)

9. Lance Glasser (12 out of 28 patents)

10. Ingo Bork (12 out of 12 patents)

11. William E Guthrie (10 out of 12 patents)

12. Takashi Mitsuhashi (10 out of 28 patents)

13. Abhishek Shendre (7 out of 7 patents)

14. Robert C Pack (6 out of 10 patents)

15. Anatoly Aadamov (5 out of 5 patents)

Core Competencies:

Lithography

Semiconductor

Bias Correction

Charged Particle Beam

Dimensional Uniformity

Optical Proximity Correction

Pattern Formation

Reticle Design

GPU Computing

Multi-Beam Lithography

Edge Slope Patterns

Sub-Resolution Features

137 patents: Sort by Forward Citations

1. 12730959 - Using a machine-trained network to perform physical design (2026-09-08),

2. 12710694 - MASK OPTIMIZATION FOR FIRST LAYER THAT ACCOUNTS FOR OTHER LAYERS (2026-08-18),

3. 12688998 - Method and system for determining a charged particle beam exposure for a local pattern density (2026-07-21),

4. 12664347 - Concurrently routing multiple partitions of an integrated circuit design (2026-06-23),

5. 12664340 - Interactively presenting for minimum overlap shapes in an IC design (2026-06-23),

6. 12656675 - Mask optimization accounting for more critical and less critical overlap regions (2026-06-16),

7. 12645858 - Generating routes for an integrated circuit design with non-preferred direction curvilinear wiring (2026-06-02),

8. 12632638 - Using pixel-based definition of an integrated circuit design to perform routing (2026-05-19),

9. 12626047 - Computing and displaying a predicted overlap shape in an IC design based on predicted misalignment of metal layers (2026-05-12),

10. 12626046 - Generating routes for an integrated circuit design with non-preferred direction curvilinear wiring (2026-05-12),

11. 12614017 - Using machine learning to produce routes (2026-04-28),

12. 12579353 - Computing parasitic values for semiconductor designs (2026-03-17),

13. 12572082 - Geometric loading effect correction for lithography (2026-03-10),

14. 12547804 - Computing and displaying a predicted overlap shape in an IC design based on predicted manufacturing contours (2026-02-10),

15. 12547803 - Leveraging concurrency to improve interactivity with an EDA tool (2026-02-10),

D2S, Inc. is a leading technology company specializing in design-to-silicon (D2S) solutions for electronic devices. With expertise in semiconductor lithography techniques, D2S offers innovative software platforms and services that optimize photomask designs and enhance manufacturing processes. Their cutting-edge solutions enable semiconductor manufacturers to achieve higher yields, reduce costs, and accelerate time-to-market for advanced integrated circuits. For more information, visit their website.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Sep 15 2026

137 Patents

#88 in San Jose, CA

#632 in California

#2,824 in US

#5,883 in the World

San Jose, CA, United States of America

D2s, Inc.

Forward Citations = 863

40 inventors:

Akira Fujimura (117 out of 141 patents)

Harold Robert Zable (26 out of 28 patents)

Nagesh Shirali (23 out of 23 patents)

4. Kazuyuki Hagiwara (15 out of 15 patents)

5. Michael Tucker (15 out of 15 patents)

Please report any incorrect information to [email protected]

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