For the Inventor, By the Inventor

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San Jose, CA, United States of America

D2s, Inc.

USPTO Granted Patents = 141

% Expired Patents = 12.1

EPO Patents = 3

Trademarks = 3

Forward Citations = 863

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40 inventors (with patents filed for the assignee):

Akira Fujimura (119 out of 145 patents)

Harold Robert Zable (26 out of 28 patents)

Nagesh Shirali (23 out of 23 patents)

4. Kazuyuki Hagiwara (15 out of 15 patents)

5. Michael Tucker (15 out of 15 patents)

6. Donald Oriordan (15 out of 17 patents)

7. P Jeffrey Ungar (14 out of 40 patents)

8. Ryan Pearman (12 out of 13 patents)

9. Lance Glasser (12 out of 28 patents)

10. Ingo Bork (12 out of 12 patents)

11. William E Guthrie (10 out of 12 patents)

12. Takashi Mitsuhashi (10 out of 28 patents)

13. Abhishek Shendre (7 out of 7 patents)

14. Robert C Pack (6 out of 10 patents)

15. Anatoly Aadamov (5 out of 5 patents)

Core Competencies:

Lithography

Semiconductor

Bias Correction

Charged Particle Beam

Dimensional Uniformity

Optical Proximity Correction

Pattern Formation

Reticle Design

GPU Computing

Multi-Beam Lithography

Edge Slope Patterns

Sub-Resolution Features

141 patents: Sort by Forward Citations

1. 12754474 - Concurrent mask optimization for multiple layers (2026-10-06),

2. 12754473 - Mask optimization preferentially accounting for overlap regions (2026-10-06),

3. 12754472 - Mask optimization for layer based on comparison of components in layer to components in other layers (2026-10-06),

4. 12754471 - Mask optimization for layer accounting for overlap with other layers (2026-10-06),

5. 12730959 - Using a machine-trained network to perform physical design (2026-09-08),

6. 12710694 - MASK OPTIMIZATION FOR FIRST LAYER THAT ACCOUNTS FOR OTHER LAYERS (2026-08-18),

7. 12688998 - Method and system for determining a charged particle beam exposure for a local pattern density (2026-07-21),

8. 12664347 - Concurrently routing multiple partitions of an integrated circuit design (2026-06-23),

9. 12664340 - Interactively presenting for minimum overlap shapes in an IC design (2026-06-23),

10. 12656675 - Mask optimization accounting for more critical and less critical overlap regions (2026-06-16),

11. 12645858 - Generating routes for an integrated circuit design with non-preferred direction curvilinear wiring (2026-06-02),

12. 12632638 - Using pixel-based definition of an integrated circuit design to perform routing (2026-05-19),

13. 12626047 - Computing and displaying a predicted overlap shape in an IC design based on predicted misalignment of metal layers (2026-05-12),

14. 12626046 - Generating routes for an integrated circuit design with non-preferred direction curvilinear wiring (2026-05-12),

15. 12614017 - Using machine learning to produce routes (2026-04-28),

D2s, Inc. is a leading innovator in the semiconductor lithography sector, headquartered in San Jose, California. The company specializes in advanced technologies that enhance the precision and efficiency of semiconductor manufacturing processes. Key areas of focus include lithography techniques, bias correction, and optical proximity correction, which are essential for achieving dimensional uniformity and optimal pattern formation in chip design. D2s, Inc. is committed to pushing the boundaries of semiconductor technology to meet the evolving demands of the industry.

Profile summary based on public USPTO records.

Company Badge

USPTO Data Jan 1 1976 - Oct 6 2026

141 Patents

#85 in San Jose, CA

#616 in California

#2,767 in US

#5,747 in the World

San Jose, CA, United States of America

D2s, Inc.

Forward Citations = 863

40 inventors:

Akira Fujimura (119 out of 145 patents)

Harold Robert Zable (26 out of 28 patents)

Nagesh Shirali (23 out of 23 patents)

4. Kazuyuki Hagiwara (15 out of 15 patents)

5. Michael Tucker (15 out of 15 patents)

Please report any incorrect information to [email protected]

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