IDiyas

For the Inventor, By the Inventor

Hsinchu, Taiwan

Zhe-Wei Jiang

USPTO Granted Patents = 21 

Average Co-Inventor Count = 5.3

ph-index = 4

Forward Citations = 165(Granted Patents)


Location History:

  • Tainan, TW (2012)
  • Hsinchu, TW (2013 - 2024)

Company Filing History:

goldMedal21 out of 40,635 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2012-2025

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21 patents (USPTO):
1. 12210811 - Layout context-based cell timing characterization (2025-01-28),
2. 12106033 - Metal cut optimization for standard cells (2024-10-01),
3. 12073162 - Capacitive isolation structure insert for reversed signals (2024-08-27),
4. 11907633 - Layout for integrated circuit and the integrated circuit (2024-02-20),
5. 11853676 - Layout context-based cell timing characterization (2023-12-26),
6. 11734481 - Metal cut optimization for standard cells (2023-08-22),
7. 11531802 - Layout context-based cell timing characterization (2022-12-20),
8. 11526649 - Capacitive isolation structure insert for reversed signals (2022-12-13),
9. 11494543 - Layout for integrated circuit and the integrated circuit (2022-11-08),
10. 11030368 - Metal cut optimization for standard cells (2021-06-08),
11. 10943050 - Capacitive isolation structure insert for reversed signals (2021-03-09),
12. 10691849 - Metal cut optimization for standard cells (2020-06-23),
13. 10685162 - Layout for integrated circuit and the integrated circuit (2020-06-16),
14. 10163883 - Layout method for integrated circuit and layout of the integrated circuit (2018-12-25),
15. 9626472 - Method and system of forming layout design (2017-04-18),

Title: Zhe-Wei Jiang: Pioneering Innovations in the World of Technology

Introduction: Zhe-Wei Jiang stands as a prominent figure in the world of innovation, with a notable track record of creating groundbreaking inventions that have left a lasting impact on the tech industry. His dedication to pushing the boundaries of technology continues to inspire aspiring inventors globally.

Latest Patents:

Zhe-Wei Jiang's latest patents include a layout for an integrated circuit and the integrated circuit, showcasing his expertise in the field of microelectronics. The layout method he devised involves intricate processes of arranging conductive paths and cut layers to optimize the performance of integrated circuits. Additionally, his layout context-based cell timing characterization method enhances the efficiency of timing analysis on integrated circuit layouts.

Career Highlights:

With a portfolio of 18 patents to his name, Zhe-Wei Jiang has demonstrated exceptional talent and ingenuity in the realm of technology. He currently works at Taiwan Semiconductor Manufacturing Company Ltd., a leading semiconductor company known for its cutting-edge innovations.

Collaborations:

Zhe-Wei Jiang has collaborated with talented individuals in his field, including coworkers Hui-Zhong Zhuang and Cheok-Kei Lei. Together, they have contributed to the development of innovative technologies and advanced the field of microelectronics.

Conclusion:

In conclusion, Zhe-Wei Jiang's contributions to the tech industry are truly commendable. His innovative spirit and dedication to advancing technology have solidified his position as a trailblazer in the world of inventions. Aspiring inventors worldwide continue to look up to him for inspiration and guidance in their own creative pursuits.

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