The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2018
Filed:
Jun. 15, 2016
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Cheok-Kei Lei, Andar AC, MO;
Yu-Chi Li, Hsinchu, TW;
Chia-Wei Tseng, Hsinchu, TW;
Zhe-Wei Jiang, Hsinchu, TW;
Chi-Lin Liu, New Taipei, TW;
Jerry Chang-Jui Kao, Taipei, TW;
Jung-Chan Yang, Taoyuan County, TW;
Chi-Yu Lu, New Taipei, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.