The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Mar. 08, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Cheok-Kei Lei, Macau, CN;

Jerry Chang Jui Kao, Taipei, TW;

Chi-Lin Liu, New Taipei, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Zhe-Wei Jiang, Hsinchu, TW;

Chien-Hsing Li, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 27/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/5223 (2013.01); H01L 27/0207 (2013.01);
Abstract

A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine the parasitic capacitance in conductive lines, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance, and operations to adjust the layout by moving a conductive line.


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