The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Nov. 30, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Cheok-Kei Lei, Hsinchu, TW;

Jerry Chang Jui Kao, Hsinchu, TW;

Chi-Lin Liu, Hsinchu, TW;

Hui-Zhong Zhuang, Hsinchu, TW;

Zhe-Wei Jiang, Hsinchu, TW;

Chien-Hsing Li, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/20 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/20 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H01L 23/5223 (2013.01); H01L 27/0207 (2013.01);
Abstract

A method of modifying an integrated circuit layout includes determining whether a first conductive line and a second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold. The method further includes adjusting the integrated circuit layout by moving the first conductive line in the integrated circuit layout in response to determining to move the first conductive line. The method further includes inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line.


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