The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2022
Filed:
May. 26, 2020
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Cheok-Kei Lei, Andar, MO;
Yu-Chi Li, Hsinchu, TW;
Chia-Wei Tseng, Hsinchu, TW;
Zhe-Wei Jiang, Hsinchu, TW;
Chi-Lin Liu, New Taipei, TW;
Jerry Chang-Jui Kao, Taipei, TW;
Jung-Chan Yang, Taoyuan County, TW;
Chi-Yu Lu, New Taipei, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.