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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Yervant Zorian

This inventor holds 48 USPTO granted patents and 1 published patent application and 1 EPO patent, primarily in Memory Testing. Top assignees: Synopsys, Inc., Virage Logic Corporation, Lucent Technologies Inc.. Active years: 1992-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yervant Zorian. Retrieved from https://idiyas.com/inventor/yervant-zorian

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 48 

% Patents Active = 95.8

 

Average Co-Inventor Count = 2.7

ph-index = 15

Forward Citations = 543(Granted Patents)


Location History:

  • Princeton, NJ (US) (1992 - 2001)
  • Santa Clara County, CA (US) (1999 - 2001)
  • Somerset, NJ (US) (2001)
  • Mountain View, CA (US) (2018 - 2022)
  • Santa Clara, CA (US) (1999 - 2024)

Company Filing History:

goldMedal23 out of 2,604 
 
Synopsys, Inc.
 patents
silverMedal12 out of 99 
 
Virage Logic Corporation
 patents
bronzeMedal5 out of 9,364 
 
Lucent Technologies Inc.
 patents
4. 3 out of 598 
 
Agere Systems Guardian Corp.
 patents
5. 2 out of 3,345 
 
At&t Bell Laboratories
 patents
6. 2 out of 4,208 
 
At+t Corp.
 patents
7. 1 out of 834,513 
Other
 patents

Years Active: 1992-2025

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Areas of Expertise:
Integrated Circuits
Memory Diagnostics
Self-Test Circuit
Fault Detection
Error Correction
Statistical Sampling
Memory Modeling
Repair Data Compression
Random Access Memories
DRAM Testing
Yield Enhancement
System-on-Chip
48 patents (USPTO):Explore Patents
1. 12469527 - In situ delay measurements on integrated circuits using live data and pulse width modulation (2025-11-11),
2. 12266413 - Built-in self-test circuit for row hammering in memory (2025-04-01),
3. 12094548 - Diagnosing faults in memory periphery circuitry (2024-09-17),
4. 12002530 - Embedded memory transparent in-system built-in self-test (2024-06-04),
5. 11527298 - On-chip memory diagnostics (2022-12-13),
6. 11023310 - Detection of address errors in memory devices using multi-segment error detection codes (2021-06-01),
7. 10789398 - Method and apparatus for SOC with optimal RSMA (2020-09-29),
8. 10192635 - FinFET-based memory testing using multiple read operations (2019-01-29),
9. 10115477 - FinFET-based memory testing using multiple read operations (2018-10-30),
10. 9831000 - Testing electronic memories based on fault and test algorithm periodicity (2017-11-28),
11. 9541591 - Periodic signal measurement using statistical sampling (2017-01-10),
12. 9514258 - Generation of memory structural model based on memory layout (2016-12-06),
13. 9336342 - Memory hard macro partition optimization for testing embedded memories (2016-05-10),
14. 9053050 - Determining a desirable number of segments for a multi-segment single error correcting coding scheme (2015-06-09),
15. 8850277 - Detecting random telegraph noise induced failures in an electronic memory (2014-09-30),

Title: The Innovative Journey of Yervant Zorian

Introduction: Yervant Zorian, a distinguished inventor based in Santa Clara, CA, has made significant contributions to the field of technology through his groundbreaking innovations and patents.

Latest Patents: Yervant Zorian holds several recent patents in the areas of semiconductor testing and design for testability, showcasing his ongoing commitment to advancing technological solutions.

Career Highlights: With a career spanning over two decades, Yervant Zorian has held key roles in leading tech companies, driving forward the development of cutting-edge technologies and pioneering new approaches to semiconductor testing.

Collaborations: Throughout his career, Yervant Zorian has collaborated with top research institutions and universities, fostering a culture of innovation and knowledge-sharing within the tech community.

Conclusion: Yervant Zorian's dedication to innovation and his remarkable contributions to the field of technology continue to inspire future generations of inventors and engineers worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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