The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Sep. 06, 2023
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Karen Darbinyan, Pleasanton, CA (US);

Yervant Zorian, Santa Clara, CA (US);

Grigor Khachatryan, Yerevan, AM;

Karen Melkonyan, Ararat, AM;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/22 (2006.01); H03K 5/15 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1066 (2013.01); G11C 7/222 (2013.01); H03K 5/15 (2013.01);
Abstract

An integrated circuit includes delay monitors that monitor the delays of data signals from the digital circuitry by generating pulses having widths determined by the delays. In some embodiments, the delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal used to clock the data signal. The pulse generator generates pulses from the received data and clock signals, where the widths of the pulses are determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay is estimable based on an overlap between the events and the pulses.


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